UNIVAC LARC
| Company type | Computer system |
|---|---|
| Industry | Computing, Supercomputing |
| Founded | June 1960 |
| Headquarters | Livermore , United States |
| Products | Mainframe computer, Supercomputer |
The UNIVAC LARC (Livermore Advanced Research Computer) was a mainframe computer engineered to fulfill Edward Teller's specifications for hydrodynamic modeling in the context of nuclear weapon development. Recognized as one of the pioneering supercomputers, it utilized solid-state electronics technology.
Its design incorporated multiprocessing capabilities, featuring two CPUs (referred to as Computers) alongside an input/output (I/O) Processor known as the Processor. Two systems were produced: the first was installed at the Livermore facility in June 1960, and the second at the Navy's David Taylor Model Basin. Both units included only a single CPU, meaning that no multiprocessor LARCs were actually deployed. The Livermore LARC was retired in December 1968, with the Navy's machine following suit in April 1969.
The LARC's CPUs executed addition operations in roughly 4 microseconds (~250 kIPS), positioning it as the fastest computer worldwide until the arrival of the IBM 7030 Stretch in 1962. Although IBM initially vied for the LARC contract, Teller preferred Univac's more straightforward design over IBM's more complex and riskier approach.
Description
The LARC functioned as a decimal mainframe employing 60-bit words and utilized bi-quinary coded decimal arithmetic, assigning five bits per digit to represent 11-digit signed numbers. Instructions were encoded in 60-bit lengths. Its standard configuration included 26 general-purpose registers, which could be expanded up to 99, each accessible within 1 microsecond.
The system weighed approximately , comprising a single Computer unit that could be extended to a multiprocessor setup by adding a second CPU. The Processor operated independently as a CPU responsible for managing between 12 and 24 magnetic drum storage devices, various tape drives, electronic page printers, high-speed line printers, and punched card readers.
Core memory was organized into banks containing 2,500 words each; the initial setup consisted of eight banks totaling 20,000 words distributed across two cabinets, with expandability up to 39 banks providing 97,500 words. Memory access time was measured at 8 microseconds with a cycle time of 4 microseconds. Through independent bank operation and interleaved memory access, effective access times were reduced to approximately 4 microseconds.
A data bus linking the two Computers and the Processor to core memory was multiplexed into eight slots of 500 nanoseconds each within every 4-microsecond cycle to optimize data throughput. Access conflicts and deadlocks were avoided by implementing priority protocols that assigned highest precedence to I/O DMA synchronizers, followed by the Processor, and then the Computers.
The LARC's Computers produced Summary Orders stored in memory for the Processor’s control software (developed by UNIVAC) to efficiently handle I/O requests.
Built using surface-barrier transistors—which were nearing obsolescence at the time—the LARC achieved addition operations in 4 microseconds, multiplication in 8 microseconds, and division in 28 microseconds. It maintained its status as the fastest computer from its introduction in 1960 until IBM's Stretch surpassed it in 1962.
LARC one-digit numeric code
The UNIVAC-LARC employed a five-bit biquinary coding scheme that allowed for up to 15 distinct combinations per digit position within storage.
| BIT POSITIONS
|
CHARACTER |
|---|---|
1 1 1 0 0
|
\ (ignore) |
0 0 1 0 0
|
^ (space) |
0 0 0 1 0
|
- (minus) |
1 0 0 0 0
|
0 |
0 0 0 0 1
|
1 |
1 0 0 1 1
|
2 |
0 0 1 1 1
|
3 |
1 0 1 1 0
|
4 |
0 1 0 0 0
|
5 |
1 1 0 0 1
|
6 |
0 1 0 1 1
|
7 |
1 1 1 1 1
|
8 |
0 1 1 1 0
|
9 |
1 1 0 1 0
|
. (period) |
1 0 1 0 1
|
+ (plus) |
See also
Further reading
External links
- Margaret R. Fox Papers, Charles Babbage Institute – contains documentation and reports related to ENIAC, UNIVAC, and LARC machines.
- Universal Automatic Computer Model LARC
- LARC Manuals and technical documents