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IBM 7030 Stretch

From Alfawiki
IBM 7030 Stretch
IndustryComputer hardware
PredecessorIBM 704
Founded1961
SuccessorIBM System/360
Key people
Stephen W. Dunwell (Project Manager)
ProductsTransistor-based supercomputer
ParentIBM

The IBM 7030, commonly known as Stretch, marked IBM's inaugural transistor-based supercomputer and held the title of the world's fastest computer from 1961 until the CDC 6600 surpassed it in 1964.

Initially created to fulfill a request from Edward Teller at the Lawrence Livermore National Laboratory, the first Stretch machine was delivered to Los Alamos National Laboratory in 1961. A customized variant, the IBM 7950 Harvest, was provided to the National Security Agency in 1962. The Stretch system installed at the Atomic Weapons Research Establishment in Aldermaston, England, became extensively utilized following the deployment of the S2 Fortran compiler, which was notable for introducing dynamic arrays; this compiler was subsequently adapted for use on the Ferranti Atlas at Chilton.

Although Stretch did not fully achieve its lofty performance objectives, IBM responded by reducing its price from $13.5 million to $7.78 million and restricting further sales to existing agreements. PC World identified the project as a significant failure in IT project management.

Within IBM, accepting the loss of leadership to smaller firms such as Control Data Corporation proved challenging. Project manager Stephen W. Dunwell initially bore the blame but was later officially exonerated and honored with an appointment as an IBM Fellow in 1966, following the successful launch of the IBM System/360.

Despite its commercial limitations, Stretch had a profound influence on numerous architectural features incorporated into the IBM System/360, which debuted in 1964 and began shipping in 1965.

Development history

In early 1955, Dr. Edward Teller from the University of California Radiation Laboratory sought a new scientific computing platform capable of performing three-dimensional hydrodynamic simulations. Both IBM and UNIVAC were invited to submit proposals for what became known as the Livermore Automatic Reaction Calculator (LARC). IBM executive Cuthbert Hurd estimated that such a system would cost approximately $2.5 million and deliver performance between one and two MIPS, with an anticipated delivery timeframe of two to three years after contract award.

At IBM's facility in Poughkeepsie, John Griffith and Gene Amdahl developed a design concept leveraging contemporary transistor technology. However, Ralph Palmer halted this effort, citing impending obsolescence due to advances in diffusion transistor technology. Consequently, IBM withdrew from the original contract and proposed instead a more advanced machine targeting ten million instructions per second, albeit with increased cost and longer development time. Livermore rejected this proposal and awarded the contract to UNIVAC in May 1955; their LARC system was delivered in June 1960.

In September 1955, anticipating potential demand from Los Alamos National Laboratory, IBM submitted an initial proposal for a high-speed binary computer based on an enhanced version of its previously declined design. This initiative evolved into Project Stretch, formally launched in January 1956. By November that year, IBM had secured a contract with an ambitious performance goal: achieving at least one hundred times the speed of the IBM 704 (approximately 4 MIPS), with delivery scheduled for 1960.

Design constraints necessitated reductions in clock frequency, making it apparent that Stretch would not fully meet its original performance targets. Projected speeds ranged between sixty and one hundred times that of the IBM 704. The final cost was set at $13.5 million in 1960. However, performance testing conducted in 1961 revealed actual throughput of roughly thirty times that of the IBM 704 (1.2 MIPS), leading to considerable disappointment within IBM. In response, Thomas J. Watson Jr. announced a price reduction to $7.78 million and discontinued further sales beyond existing contracts.

The floating-point operation timings on the IBM 7030 included addition requiring between 1.38 and 1.50 microseconds, multiplication taking from 2.48 up to 2.70 microseconds, and division operations lasting between 9.00 and 9.90 microseconds.

Technical impact

Despite the IBM 7030's lack of commercial success, it played a crucial role in pioneering technologies that shaped numerous subsequent IBM systems. The use of Standard Modular System (SMS) transistor logic in the 7030 laid the groundwork for the IBM 7090 scientific computers, as well as the business-oriented IBM 7070 and IBM 7080, alongside the IBM 7040, IBM 1400 families, and the smaller scientific IBM 1620. Approximately transistors were integrated into the 7030. Additionally, the IBM 7302 Model I Core Storage modules found applications in the IBM 7090, 7070, and 7080 models. Innovations such as multiprogramming, memory protection mechanisms, generalized interrupt handling, and the adoption of an eight-bit byte for input/output operations were later incorporated into the IBM System/360 series and became standard features in most following central processing unit designs.

Stephen Dunwell, who managed the Stretch project and initially bore responsibility for its market shortcomings, emphasized that many foundational ideas behind the highly successful 1964 launch of System/360 originated with Stretch. By 1966, Dunwell received formal recognition and an apology from IBM, being appointed an IBM Fellow with resources to pursue further research.

Advanced techniques first implemented in Stretch—including instruction pipelining, prefetching combined with decoding, and memory interleaving—influenced later supercomputers such as IBM System/360 Models 91, 95, 195, and the IBM 3090 series. As of 2021, these approaches remain integral to cutting-edge microprocessors like Intel’s Pentium and Motorola/IBM’s PowerPC, as well as numerous embedded microcontrollers and microprocessors.

Hardware implementation

The CPU of the 7030 utilizes emitter-coupled logic—initially termed current-steering logic—across eighteen variants of Standard Modular System cards. The architecture comprises 4,025 double-width and 18,747 single-width cards, containing a total of approximately 169,100 transistors while consuming around 21 kW of electrical power. High-speed NPN and PNP germanium drift transistors with cut-off frequencies exceeding 100 MHz are employed, each transistor drawing roughly 50 mW. Certain circuits operate with three voltage levels; typical logic gate delays are near 20 nanoseconds, whereas critical signal paths utilize emitter-follower logic to reduce delays to approximately 10 nanoseconds.

The memory design follows principles established by the IBM 7090, employing core memory technology.

Installations

  1. Los Alamos Scientific Laboratory (LASL), active from April 1961 until June 1971.
  2. Lawrence Livermore National Laboratory, installation completed November 1961.
  3. U.S. National Security Agency, February 1962; functioned as the primary CPU for the IBM 7950 Harvest system up to 1976.
  4. Atomic Weapons Establishment, located in Aldermaston, England; operational from February 1962.
  5. U.S. Weather Bureau in Washington D.C., installed June/July 1962.
  6. MITRE Corporation, commissioned December 1962; remained in service until August 1971 before being sold to Brigham Young University for physics experiments until dismantled in 1982.
  7. U.S. Navy Dahlgren Naval Proving Ground, installed September/October 1962.
  8. Commissariat à l'énergie atomique, France; installed November 1963.
  9. IBM.

Portions of the Lawrence Livermore Laboratory’s IBM 7030 system (excluding core memory) along with components from the MITRE/Brigham Young units are preserved at the Computer History Museum in Mountain View, California.

Data formats

  • Fixed-point numbers come in varying lengths, stored either in binary form (ranging from 1 to 64 bits) or decimal form (from 1 to 16 digits), utilizing unsigned or sign/magnitude representation. These fields can span across word boundaries. Decimal digits are encoded as variable-length bytes between 4 and 8 bits.
  • Floating-point numbers are structured with a 1-bit exponent flag, a 10-bit exponent, a 1-bit exponent sign, a 48-bit magnitude, and a 4-bit sign byte arranged in sign/magnitude format.
  • Alphanumeric characters support variable lengths and accommodate any character code up to 8 bits.
  • Byte sizes vary from one to eight bits.

Instruction format

Instructions are available in either 32-bit or 64-bit lengths.

Registers

The initial 32 memory addresses correspond to registers as detailed below:

! Address Mnemonic Register Description Storage Location
0 $Z A 64-bit zero register that always reads zero and cannot be altered Main core storage
1 $IT Interval timer occupying bits 0–18; decrements at 1024 Hz and signals when reaching zero Index core storage
$TC A 36-bit time clock spanning bits 28–63; counts ticks at 1024 Hz, increments every second, with a cycle duration of approximately 777 days
2 $IA An 18-bit interruption address register Main core storage
3 $UB Upper boundary address (18 bits: bits 0–17) Transistor register
$LB Lower boundary address covering bits 32–49 (18 bits)
Boundary control bit located at bit 57; governs protection of addresses inside or outside boundaries
4 A set of system maintenance bits totaling 64 bits, reserved for internal use Main core storage
5 $CA Channel address occupying bits 12–18; read-only and set by I/O processor through "exchange" Transistor register
6 $CPUS CPU cluster signaling bits (bits 0–18) supporting up to twenty CPUs Transistor register
7 $LZC Left zero count representing leading zeros in connective or floating-point results (bits 17–23) Transistor register
$AOC All-ones count indicating set bits in connective results or decimal operations (bits 44–50)
8 $L Left half of the 128-bit accumulator Transistor register
9 $R Right half of the accumulator
10 $SB Sign byte of the accumulator covering bits 0–7
11 $IND Indicator register containing bits 0–19 Transistor register
12 $MASK A mask register of 64 bits: bits 0–19 are permanently set, bits 20–47 writable, and bits 48–63 cleared Transistor register
13 $RM Remainder register utilized exclusively for integer and floating-point division operations Main core storage
14 $FT Factor register modified solely by the "load factor" instruction Main core storage
15 $TR Transit register with a width of 64 bits Main core storage
16...31 $X0...$X15 Sixteen index registers each consisting of 64 bits Index core storage

Both the accumulator and index registers employ sign-and-magnitude representation.

Memory

Primary memory capacity ranged between 16K and 256K words of 64-bit binary data, arranged in banks of 16K words. To maintain stable operation, immersion oil was used for heating and cooling purposes.

Software

  • STRETCH Assembly Program (STRAP)
  • MCP (a system distinct from the Burroughs MCP)
  • Programming languages COLASL and IVY
  • FORTRAN language
  • SOS (Stretch Operating System), created at BYU Scientific Computing Center as an enhancement to MCP, featuring an updated FORTRAN version

See also

  • IBM 608, recognized as the first transistor-based computing machine made commercially accessible
  • ILLIAC II, a transistor-equipped supercomputer developed by the University of Illinois that served as a competitor to Stretch

Further reading

External links

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