UltraSPARC II
| Company type | Microprocessor |
|---|---|
| Industry | Semiconductor |
| Founded | 1997 |
| Founder | Marc Tremblay (lead architect) |
| Products | Microprocessors implementing SPARC V9 ISA |
| Parent | Sun Microsystems |
The UltraSPARC II, internally known as "Blackbird," is a microprocessor that executes the SPARC V9 instruction set architecture (ISA). Developed by Sun Microsystems with Marc Tremblay serving as the lead architect, it debuted in 1997. This processor enhanced the original UltraSPARC design by supporting clock frequencies ranging from 250 MHz up to 650 MHz.
Manufactured by Texas Instruments using a 0.35 μm fabrication technology, its chip contained approximately 5.4 million transistors within an area of 149 mm². At 205 MHz and powered by a 2.5 V supply, it consumed 25 W and accommodated between 1 and 4 MB of L2 cache.
In 1999, the UltraSPARC II was refined with a shift to a 0.25 μm process node, referred to as "Sapphire-Black." This revision allowed clock speeds to increase to the range of 360–480 MHz, reduced the die size to 126 mm², decreased power consumption to 21 W at 400 MHz, and lowered operating voltage to 1.9 V. Additionally, the L2 cache capacity was expanded to between 1 and 8 MB.
Derivatives
The UltraSPARC II architecture gave rise to four distinct derivative models.
UltraSPARC IIi
Released in 1997, the UltraSPARC IIi, codenamed "Sabre," was designed as an economical alternative featuring an integrated PCI controller on-chip. It operated at clock rates from 270 to 360 MHz and was produced using a 0.35 μm manufacturing process with a die size of 156 mm². Power dissipation stood at 21 W with a voltage of 1.9 V, and L2 cache sizes ranged from 256 KB up to 2 MB. In 1998, the "Sapphire-Red" update transitioned this model to a finer 0.25 μm process, enabling higher frequencies between 333 and 480 MHz while maintaining similar power characteristics.
UltraSPARC IIe
Targeting embedded system applications, the UltraSPARC IIe "Hummingbird" was introduced in 2000. It operated within a frequency band of 400–500 MHz and was fabricated using a 0.18 μm process featuring aluminium interconnects. The processor’s power consumption peaked at approximately 13 W at maximum speed, with a supply voltage ranging from 1.5 to 1.7 V. It incorporated a dedicated 256 KB L2 cache.
UltraSPARC IIe+
Known also as IIi and released in 2002 under the code name "Phantom," this variant ran at frequencies between 550 and 650 MHz. Utilizing a more advanced 0.18 μm process with copper interconnect technology, it drew about 17.6 W at a voltage of 1.7 V and included a larger L2 cache of 512 KB.
Gemini
Gemini represented Sun's first attempt at creating a multithreaded microprocessor design. Although the chip reached tape-out stage, its launch was ultimately canceled following the announcement of the UltraSPARC T1 Niagara in early 2004. This processor combined two UltraSPARC II cores on a single die alongside integrated L2 cache.
Presented at DAC in 2004, this dual-core UltraSPARC II featured several enhancements: a DDR-1 memory controller, JBUS interface, parity-protected L1 caches, ECC-protected dual on-chip L2 caches each sized at 512 KB, operated at a clock speed of 1.2 GHz, contained roughly 80 million transistors within a die area of approximately 206 mm², and consumed about 23 W—specifically engineered for high-density server environments.