UltraSPARC T2
| Industry | Computer hardware |
|---|---|
| Founded | February 24, 1982 |
| Fate | Acquired by Oracle Corporation in 2010 |
| Headquarters | Santa Clara, California , United States |
| Products | Microprocessors, Servers, Software |
Sun Microsystems' UltraSPARC T2 microprocessor represents a multithreaded, multi-core CPU within the SPARC lineup, succeeding the UltraSPARC T1. Nicknamed Niagara 2, Sun started offering servers equipped with the T2 processor in October 2007.
New features
Designed to handle Internet-centric tasks spanning computing, storage, and networking, the T2 is fabricated using a 65 nm technology. It incorporates eight cores, each capable of running eight threads simultaneously, resulting in support for up to 64 concurrent threads. Notable improvements include:
- Boosted thread frequency from 1.2 GHz up to 1.6 GHz
- Introduction of a single PCI Express port (x8 1.0), replacing the JBus interface found in the T1
- Integration of two Sun Neptune 10 Gigabit Ethernet ports featuring packet classification and filtering capabilities
- Enlarged L2 cache size increased to 4 MB (comprising 8 banks with 16-way associativity) from the previous 3 MB
- Upgraded thread scheduling and instruction prefetch mechanisms to enhance single-thread efficiency
- Each core now contains two integer ALUs shared by four threads, doubling the count from one ALU per core
- Addition of one floating point unit per core, an increase over the single FPU for the entire chip in the predecessor
- Eight dedicated encryption engines supporting algorithms such as DES, Triple DES, AES, RC4, SHA1, SHA256, MD5, RSA-2048, ECC, and CRC-32
- Built-in hardware random number generator
- Four dual-channel FBDIMM memory controllers
Core pipeline
The UltraSPARC T2 employs an 8-stage integer pipeline architecture, compared to the six stages utilized in the T1.
| Processor | Pipeline Stages | |||||||
|---|---|---|---|---|---|---|---|---|
| T1 Pipeline | Fetch | <math>\longrightarrow</math> | Thread Selection | Decode | Execute | Memory Access | <math>\longrightarrow</math> | Writeback |
| T2 Pipeline | Fetch | Cache | Thread Selection | Decode | Execute | Memory Access | Bypass | Writeback |
Systems
The T2 processor serves as the core of multiple Sun and Fujitsu Computer Systems products, including:
- Sun/Fujitsu/Fujitsu Siemens SPARC Enterprise T5120 and T5220 servers
- Sun Blade T6320 Server Module
- Sun Netra CP3260 Blade
- Sun Netra T5220 Rackmount Server
Additionally, Sun licensed the T2 design to Themis Computer, which launched the first non-Sun server based on this processor in 2008:
- Themis T2BC Blade Server compatible with IBM BladeCenter chassis
UltraSPARC T2 Plus
In April 2008, Sun unveiled the UltraSPARC T2 Plus, an SMP-enabled advancement of the UltraSPARC T2. Major updates comprised:
- Capability for dual- and quad-processor setups—marking it as the first CoolThreads CPU with multi-processor support
- Omission of the integrated 10 Gigabit Ethernet controller present on-chip
T2 Plus systems
Systems featuring UltraSPARC T2 Plus processors include these Sun and Fujitsu models:
Two-processor SMP servers:
- SPARC Enterprise T5140
- SPARC Enterprise T5240
Four-processor SMP server:
- SPARC Enterprise T5440
Compute cluster
Canada’s High Performance Computing Virtual Laboratory constructed a cluster utilizing 78 SPARC Enterprise T5140 servers. Each system contains two 1.2 GHz T2 Plus processors, collectively delivering nearly 10,000 compute threads optimized for high-throughput applications.
Virtualization
Similar to the T1, the T2 incorporates support for Hyper-Privileged execution mode. Operating within this mode, the SPARC Hypervisor enables partitioning of a T2 system into up to 64 Logical Domains, while a dual-processor SMP T2 Plus system can be divided into 128 Logical Domains. Each domain functions as a separate operating system environment.
Performance improvements compared to T1
The UltraSPARC T2 offers notable enhancements in performance over its predecessor, the UltraSPARC T1:
- More than double the integer throughput and throughput per watt
- Single-thread integer performance improved by over 40%
- Floating-point throughput increased by a factor exceeding ten
- Single-thread floating-point performance raised by over five times
- Cryptographic capabilities enhanced with additional cipher support integrated into the crypto cores
- Set two world records for single-chip SPEC CPU benchmarks: achieving 78.5 SPECint_rate2006 and 62.3 SPECfp_rate2006
Further details on performance tuning of the UltraSPARC T2 can be found in technical blogs authored by Oracle engineers.
Power consumption
The maximum power draw of the T2 reaches approximately 123 watts, with typical operation around 95 watts. This is higher than the T1’s peak of 72 watts, reflecting the increased on-chip integration present in the T2 design.
Release timeline
Sun Microsystems announced the tape-out of the UltraSPARC T2 on April 12, 2006. The processor officially launched on August 7, 2007, marketed as "the world's fastest microprocessor." Subsequently, on April 9, 2008, Sun unveiled the UltraSPARC T2 Plus model.
Open design initiative
On December 11, 2007, Sun made the UltraSPARC T2 processor design available under the GNU General Public License through the OpenSPARC project. This open-source release package contains:
- Verilog RTL source files
- Verification frameworks and diagnostic test suites
- Simulation tools and automation scripts
- ISA documentation (UltraSPARC Architecture 2007)
- Simulation images for Solaris 10