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UltraSPARC T1

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Sun Microsystems
IndustryComputer hardware
FoundedFebruary 24, 1982; 44 years ago (1982-02-24) in Santa Clara, California, United States
FounderVinod Khosla, Andy Bechtolsheim, Bill Joy, Scott McNealy
Headquarters
Santa Clara, California
,
United States
ProductsUltraSPARC T1 microprocessor

The UltraSPARC T1 (internally known as "Niagara") is a multicore, multithreaded CPU launched by Sun Microsystems in 2005. Engineered to minimize power consumption in server environments, it typically operates at 1.4 GHz while consuming approximately 72 watts.

Built from the ground up to adhere to the UltraSPARC Architecture 2005 standard, the T1 implements the complete SPARC V9 instruction set. Although Sun had previously introduced multicore processors such as the UltraSPARC IV and IV+, the UltraSPARC T1 was their initial design to integrate both multicore and multithreading capabilities. It incorporates dedicated hardware cryptographic engines, providing enhanced security features beyond those of typical general-purpose CPUs at the time. Offered in configurations with four, six, or eight cores, each core supports four threads simultaneously, allowing for up to 32 threads to run concurrently.

The UltraSPARC T1 supports partitioning akin to high-end Sun SMP systems, enabling the assignment of specific cores to designated processes or thread groups for improved workload distribution.

Production history

The foundation for Sun’s CoolThreads processor family originated from Afara Websystems, which developed a SPARC processor architecture focused on heavy threading. Following its acquisition by Sun, this design approach culminated in the UltraSPARC T1.

Cores

The UltraSPARC T1 was conceived as a multithreaded processor optimized for high thread concurrency and efficient pipeline use rather than complex individual core architectures. Its streamlined cores permit eight cores per chip but omit features such as out-of-order execution and large cache hierarchies.

Instead of relying on expansive caches to handle latency from cache misses—as is common in single-thread processors—the T1 employs a barrel processor design that cycles through multiple threads each clock cycle. When a thread encounters a long-latency event like a cache miss, it is suspended while waiting for data retrieval, allowing other threads to execute without delay and maintaining high throughput despite smaller cache sizes.

This architectural approach performs exceptionally well on commercial multithreaded integer workloads including Java application servers, enterprise resource planning (ERP) systems, email platforms such as Lotus Domino, and web hosting servers. Performance benchmarks demonstrate that each UltraSPARC T1 core surpasses the single-core UltraSPARC III processors from around 2001 and offers superior multithreaded integer processing compared to contemporaneous alternatives.

Physical characteristics

Containing 279 million transistors within a die measuring 378 mm2, the UltraSPARC T1 was manufactured by Texas Instruments utilizing a 90 nm complementary metal–oxide–semiconductor (CMOS) fabrication process with nine layers of copper interconnect. Each core includes 16 KB of L1 instruction cache and 8 KB of L1 data cache, supported by a shared 3 MB L2 cache; there is no L3 cache present.

Systems

Various Sun and Fujitsu systems incorporate the T1 processor, including:

Target market

The UltraSPARC T1 is engineered primarily for servers that manage network traffic and high concurrency, rather than for systems focused on intensive numerical computations. It is tailored to efficiently support busy web server environments as well as mid-level Java, ERP, and CRM application servers that must process a large number of simultaneous threads. A notable constraint is its use of a single floating point unit (FPU) shared among all eight cores, which limits its effectiveness for workloads heavily reliant on floating-point calculations. Nevertheless, this design choice aligns well with the typical demands of its target sectors, where extensive floating-point processing is uncommon. To help determine whether applications are a good fit for the T1 or T2 platforms, Sun provides an evaluation tool that analyzes parallelism and floating-point operation usage.

In addition to web and application layers, the UltraSPARC T1 is also suitable for smaller-scale database applications serving substantial user populations; one example demonstrated a MySQL workload achieving performance 13.5 times faster on a T1 compared to an AMD Opteron system.

Virtualization

The UltraSPARC T1 was the first SPARC processor to incorporate Hyper-Privileged execution mode, which allows the SPARC Hypervisor to divide a single physical system into as many as 32 Logical Domains. Each domain can run its own independent operating system instance.

As of March 2021, supported operating systems include Solaris, Linux, NetBSD, and OpenBSD.

Software licensing issues

Traditional commercial software packages such as Oracle Database have historically licensed products based on the number of processors. In 2006, Oracle introduced the processor factor concept, whereby an 8-core T2000 system with a factor of 0.25 requires only a 2-CPU license. The "Oracle Processor Core Factor Table" has been periodically updated to account for new CPU models.

In the third quarter of 2006, IBM implemented Value Unit (VU) pricing, assigning each T1 core 30 PVUs (with T2 cores rated at 50 PVUs and T3 cores at 70 PVUs) instead of the standard 100 PVUs per core.

Weaknesses

The limitation of having just one floating-point unit shared across eight cores constrained the UltraSPARC T1’s suitability for high-performance computing (HPC) tasks. This shortcoming was remedied in the UltraSPARC T2, which introduced eight dedicated floating-point units along with other improvements.

The T1 was restricted to uniprocessor configurations, limiting its vertical scalability in enterprise settings. This capability was enhanced in subsequent models such as the UltraSPARC T2 Plus, SPARC T3, and SPARC T4, all of which support single, dual, and quad-socket arrangements.

While the T1 delivered exceptional throughput under heavy multithreaded workloads, some single-threaded applications experienced performance bottlenecks. The SPARC T4 addressed this by reducing core count from 16 in the T3 to 8 cores but increasing core complexity and nearly doubling clock speeds, resulting in a 300% to 500% improvement in single-thread performance. Furthermore, the introduction of the "critical thread API" allowed the operating system to temporarily dedicate an entire core’s resources to CPU-bound single-threaded tasks, effectively resolving bottlenecks without sacrificing throughput for multithreaded processing.

Contemporary and subsequent designs

The "Coolthreads(TM)" microarchitecture launched with the UltraSPARC T1 played a pivotal role in shaping both concurrent and future SPARC processor developments.

"Rock"

The UltraSPARC T1 was confined to single-processor configurations lacking SMP functionality. The "Rock" initiative sought to enable multi-chip server designs tailored for conventional data-intensive applications such as database management. Intended as the next generation following Sun's SMP processors like the UltraSPARC IV, rather than a direct successor to the T1 or T2, the "Rock" project was discontinued around the period when Oracle acquired Sun.

UltraSPARC T2

Initially known as Niagara 2 during its development phase, the UltraSPARC T2 increased its core count to eight. Each core supports eight simultaneous threads, integrates a single floating-point unit, features an upgraded cryptographic engine, and incorporates built-in 10 Gigabit Ethernet controllers, collectively improving both processing power and network connectivity compared to the T1.

UltraSPARC T2 Plus

Unveiled in February 2007 under the codename Victoria Falls, this third-generation simultaneous multithreading processor was finalized in October 2006. A dual-socket (2 RU) server configuration provides 128 threads spread over 16 cores, delivering a performance enhancement of approximately 65 times relative to the UltraSPARC III.

At Hot Chips 19, Sun announced that Victoria Falls would be available in both two-way and four-way server models, supporting up to 256 hardware threads concurrently within a single quad-socket SMP system.

In April 2008, Sun introduced two-way UltraSPARC T2 Plus servers: the SPARC Enterprise T5140 and T5240. Subsequently, in October 2008, the four-way UltraSPARC T2 Plus SPARC Enterprise T5440 was launched, focusing on midrange enterprise workloads with competitive pricing and energy efficiency.

SPARC T3

First revealed in October 2006, Niagara 3 (later named SPARC T3) utilized a 45 nm semiconductor process. Mid-2008 reports projected a design featuring 16 cores; this was confirmed at Hot Chips 21 where Sun disclosed the processor contains 16 cores supporting a total of 128 threads.

As detailed in the ISSCC 2010 presentation:

"A 16-core SPARC system-on-chip processor supports up to 512 threads in a four-way glueless configuration to maximize throughput. It includes a 6 MB L2 cache with a bandwidth of 461 GB/s and a 308-pin SerDes I/O interface delivering 2.4 Tb/s data rates. The design incorporates six clock domains and four voltage domains, alongside power management strategies that enhance performance, energy efficiency, manufacturing variability tolerance, and yield across its 377mm2 die."

SPARC T4

Launched in late 2011, the SPARC T4 processor reduced its core count from sixteen (as in the T3) down to eight, aligning more closely with earlier models such as the T1, T2, and T2+. Its new "S3" core introduced out-of-order execution capabilities that markedly improved both single-thread and per-thread performance. In 2010, Larry Ellison announced Oracle Linux support for the UltraSPARC architecture, aiming for availability alongside the T4 and T5 processors. By OpenWorld 2014, Oracle confirmed that Linux compatibility on SPARC platforms had been achieved.

SPARC T5

The SPARC T5 processor incorporates 16 cores and supports 128 simultaneous threads, utilizing 28nm fabrication technology to enhance both speed and energy efficiency.

Open design

On March 21, 2006, Sun Microsystems made the UltraSPARC T1 processor architecture publicly available under the GNU General Public License through the OpenSPARC initiative. This project provides access to:

  • The Verilog source code for the UltraSPARC T1;
  • A comprehensive verification suite along with simulation models;
  • The UltraSPARC Architecture 2005 Instruction Set Architecture (ISA) documentation;
  • Simulation images of the Solaris 10 operating system.

External links

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