VAX 9000
| Company type | Mainframe computer series |
|---|---|
| Industry | Computer hardware |
| Predecessor | VAX 8800 series |
| Founded | 1986 |
| Founder | Digital Equipment Corporation (DEC) |
| Fate | Discontinued |
| Headquarters | Hudson Fab (development location) , United States |
Area served | Mainframe and supercomputer markets |
Key people | Ken Olsen (CEO), Bob Glorioso (project leader) |
| Products | Mainframe computers with ECL-based processors, optional vector processor units |
The VAX 9000 represents a now-obsolete mainframe series created by Digital Equipment Corporation (DEC), incorporating bespoke ECL-based processors that execute the VAX instruction set architecture (ISA). Equipped optionally with vector processor units, the VAX 9000 was engineered to serve both the high-end mainframe and supercomputer sectors. It supported operation under either the VMS or Ultrix operating environments.
Initiated in 1986, development followed DEC’s acquisition of technology rights from Trilogy Systems, which facilitated the compact integration of ECL chips. The VAX 9000 was intended as the successor to the advanced VAX 8800 series. The original plan featured two variants: a high-performance water-cooled version called Aquarius and a midrange air-cooled model named Aridus. Advances in air cooling technology led to the discontinuation of Aquarius; meanwhile, Aridus units were designed for field upgrades, but Aquarius never reached market release.
Marketed as an "IBM competitor," the VAX 9000 sought to provide enhanced performance at a reduced cost, signaling DEC’s return to the mainframe arena after its 1983 withdrawal. This initiative was also aimed at challenging IBM PC compatibles and the rising dominance of 32-bit Unix workstations in lower-tier markets. Despite internal skepticism amid growing RISC competition, DEC invested approximately $1 billion into the project. However, delays in production enabled newer microprocessors, including DEC’s own NVAX, to deliver similar performance levels at much lower prices.
Fewer than fifty units were ultimately shipped before production ended, marking a notable commercial setback. Some CPU examples are preserved in collections at the Computer History Museum and Large Scale Systems Museum.
DEC in the 1980s
During the 1980s, DEC leveraged the success of its PDP-11 line, which achieved sales of 600,000 units, alongside the VAX-11 series that competed effectively against IBM’s midrange offerings. The company also gained revenue from its VT100 terminals and assorted peripheral devices.
Despite efforts to penetrate the personal computer market with products such as the Rainbow 100—which aimed to operate both MS-DOS and CP/M but underperformed—DEC eventually retreated from PCs to concentrate on midrange systems.
This strategic realignment resulted in policy decisions that distanced customers and third-party developers. For instance, DEC limited access to its new VAXBI Bus exclusively to licensed developers, diverging from the open Unibus standard that had fostered a vibrant third-party ecosystem. Ken Olsen acknowledged substantial investment in this bus but expressed reservations about its closed nature.
Meanwhile, competitors like Sun Microsystems exploited DEC's restrictive approach by offering Motorola 68000-based systems running UNIX that rivaled DEC’s VAXstations. By the late 1980s, Sun had established itself as a technical alternative in the market while DEC shifted focus toward data center segments with higher profit margins starting in 1985.
ECL
Throughout the 1960s and 1970s, DEC transitioned from transistor-based designs toward small scale integration (SSI) integrated circuits and later large scale integration (LSI), enabling more compact CPUs such as the LSI-11 and J-11 for the PDP-11 platform. Early VAX models similarly utilized multiple LSI chips mounted on circuit boards; by the mid-1980s, very large scale integration (VLSI) technology allowed single-chip VAX CPUs like the CVAX introduced in 1987.
Anticipating desktop-sized VAX systems at reduced costs, DEC explored options for high-performance machines beyond CMOS technology. They examined emitter-coupled logic (ECL), which offered speed advantages but demanded more chips and intricate interconnections due to lower packing density and larger feature sizes.
In 1980, Gene Amdahl founded Trilogy Systems to tackle challenges in ECL mainframe manufacturing by introducing innovations such as copper inter-chip wiring embedded within polyimide insulation for dense circuit routing. DEC licensed Trilogy’s technology in 1984 to create a high-performance VAX system at Hudson Fab—known internally as project 9000. Unlike Trilogy’s IBM-compatible mainframes, DEC pursued superior performance at reduced cost using multi-chip units (MCUs); ultimately, each CPU consisted of thirteen MCUs operating collectively.
The initial design required water cooling (codenamed Aquarius), but development later shifted toward an air-cooled variant named Aridus ("dry"), consistent with DEC’s use of Greek-inspired codenames for projects during this period.
Market shifts
Towards the end of 1988, IBM introduced its AS/400 midrange lineup, aggressively pricing it below DEC's offerings and effectively halting DEC’s rapid expansion in the market. The AS/400 series eventually generated annual revenues around $14 billion, surpassing DEC’s total company income. At the same time, Sun Microsystems unveiled the SPARC microprocessor, which empowered desktop computers to outperform DEC’s fastest machines, eroding DEC’s standing within the Unix sector. Facing competitive pressure in both low-end and midrange markets, DEC redirected its efforts toward the 9000 series, marketing it as the "IBM killer."
Initially doubtful about RISC technology—considering it suitable only for lightweight applications—DEC reversed its stance in 1986 after a RISC design from its Western Research Lab demonstrated twice the performance of the VAX 8800. This breakthrough led to the creation of the scalable RISC-based DEC PRISM. Dave Cutler, responsible for PRISM’s high-end design, encountered conflicts with the Aridus team, who felt their territory was being infringed upon. Despite repeated recommendations from the Strategy Task Force to terminate Aridus, project leader Bob Glorioso appealed directly to CEO Ken Olsen and the board, arguing that engineering teams should not make strategic business decisions.
Meanwhile, the CMOS group continued advancing VAX processors with the NVAX, which by 1987 was projected to match the 9000’s performance by 1988—prior to the 9000’s planned debut in 1989. Senior engineers cautioned Olsen that the 9000 would soon lose competitiveness; however, he declined to abandon the project or heed these warnings.
Although support for the faltering 9000 endured, various internal RISC initiatives multiplied but were ultimately discontinued, save for limited low-end PRISM development at Hudson Fab.
Launch
DEC officially unveiled the 9000 in October 1989, positioning it as a cost-effective alternative to IBM’s premier mainframe, the IBM 3090, aimed at transaction processing and high-end database workloads. The launch included five models priced between $1.2 million and $3.9 million, offering performance levels from 30 to 117 times that of the 11/780.
Development expenses approached $3 billion. Although initially scheduled for release in 1989, delays in chip production postponed shipments until 1990, with only minimal deliveries completed. The systems experienced frequent maintenance problems; by 1991 only about 350 units had been sold. At $1.5 million apiece, revenue recovered just a quarter of development costs—excluding manufacturing expenses. In February 1991, DEC introduced a more affordable Model 110 priced at $920,000 for customers requiring CPU capacity without extensive storage.
Simultaneously, CMOS technology advanced swiftly. By 1991, NVAX processors delivered similar performance at significantly reduced size and cost, including desktop models outperforming earlier VAX systems. The 9000 not only generated substantial financial losses but also led to cancellation of several promising projects.
Strategic realignment
By 1991, perceptions of the 9000 had shifted toward viewing it as stalled and underwhelming. In August of that year, division head Glorioso left DEC citing family reasons.
In October 1991, DEC restructured the division into the Production System Business Unit and implemented a 30% price cut on existing 9000 models alongside a 38% reduction on related server software. They announced three CMOS-based models—the 9X15, 9600, and 9800—none of which reached customers. Existing clients were offered discounted upgrades to new DEC Alpha-based platforms.
Further difficulties emerged in early 1992 when reports indicated hardware failures affected roughly 37% of installed units, primarily impacting the 9420 models. While service support and compatibility with other DEC products received positive remarks, overall reliability and cost effectiveness remained poorly rated.
Description
The VAX 9000 was engineered as a multiprocessor platform capable of supporting between one and four CPUs operating at 62.5 MHz (16 ns cycle duration). At its core, a crossbar switch within the system control unit (SCU) linked up to four processors, two memory controllers, two input/output controllers, and a service processor. Input/output operations were managed through four Extended Memory Interconnect (XMI) buses.
Scalar processor
Each central processing unit consisted of 13 Multi-Chip Units (MCUs), each incorporating multiple emitter-coupled logic (ECL) macrocell arrays responsible for CPU logic functions. These gate arrays were produced using Motorola’s "MOSAIC III" bipolar fabrication process, featuring a 1.75-micrometer drawn line width and three layers of interconnects. The MCUs were assembled onto a CPU planar module measuring 24 by 24 millimeters.
Vector processor
Included within the VAX 9000 was a vector processing unit known as the V-box, capable of achieving up to 125 MFLOPS. While this vector unit was integrated into every system, it was disabled through software on models lacking vector processing support. The V-box represented Digital’s initial use of ECL technology to implement the VAX Vector Architecture, with its design commencing in 1986—two years following the start of CPU development.
The vector processor comprised 25 Motorola Macrocell Array III devices distributed among three MCUs on the planar module. It contained six functional subunits: vector register, addition, multiplication, masking, addressing, and control.
The vector register subunit included 16 multi-ported vector registers, each equipped with three write ports and five read ports. Each register held 64 elements, each element being 72 bits wide—64 bits allocated for data and an additional 8 bits for parity—meeting the specifications of the VAX vector architecture.
SID (Synthesis of Integral Design) was an advanced logic synthesis tool responsible for generating logic gates in the VAX 9000 design. It synthesized roughly 93% of both scalar and vector CPU components—amounting to over 700,000 gates—from high-level behavioral descriptions and register-transfer level models.
Operating as an artificial intelligence rule-driven expert system with more than 1,000 manually crafted rules, SID extended beyond simple gate generation to wiring-level design tasks. It assigned load values to nets and supplied parameters necessary for place-and-route computer-aided design tools. Over time, its rule base expanded dramatically to encompass approximately 384,000 low-level rules. A full synthesis cycle required around three hours to complete.
SID’s AI algorithms produced designs that outperformed individual expert engineers by effectively balancing multiple design criteria such as physical size and timing constraints. Specialists contributed targeted rules aimed at optimizing for performance, minimizing area, or enhancing wiring efficiency. Through iterative passes that resolved conflicts among these rules, SID achieved an optimal balance in the final design.
Significantly, SID was pioneering as the first AI program capable of self-modification and self-learning by generating new rules derived from expert feedback. Although initially met with skepticism, it was ultimately employed to reduce costs within the VAX 9000 project. Despite early doubts, SID’s outputs equaled or surpassed manual designs regarding area efficiency and timing performance. For example, SID created a 64-bit adder circuit faster than those designed manually and exhibited substantially lower defect rates—approximately one error per 20,000 gates compared to one per 200 gates in manual designs. Corrections applied to SID’s rule set eliminated these errors in subsequent iterations.
The portion of the VAX 9000 developed using SID was completed two years ahead of schedule, contrasting with delays experienced in other segments of the project. Nevertheless, SID was not utilized in later Digital projects.
VAX 9000 Model 110
The VAX 9000 Model 110 served as the entry-tier option, delivering performance comparable to the Model 210 but featuring reduced memory capacity and a more limited set of included software and services. As of 22 February 1991, its base price was US$920,000, increasing to US$997,000 when equipped with a vector processor.
VAX 9000 Model 210
The Model 210 was designed with a single CPU configuration that could be upgraded. When fitted with a vector processor, it was referred to as the VAX 9000 Model 210VP.
VAX 9000 Model 4x0
The Model 4x0 series of the VAX 9000 supported multiprocessing capabilities, where "x" (ranging from 1 to 4) indicated the number of CPUs installed. Each CPU had the option to include one vector processor. The maximum supported memory was 512 MB. I/O bus configurations differed by model: Models 410 and 420 were equipped with two XMI buses, ten CI buses, and eight VAXBI buses; Models 430 and 440 featured four XMI buses, ten CI buses, and fourteen VAXBI buses.