NVAX
| Industry | Computer hardware |
|---|---|
| Founded | November 12, 1957 |
| Founder | Ken Olsen, Harlan Anderson |
| Headquarters | Maynard, Massachusetts , United States |
| Products | NVAX microprocessor series, VAX computers, DECchip 21064 |
The NVAX represents a CMOS microprocessor created by Digital Equipment Corporation (DEC) that implements the VAX instruction set architecture (ISA). Its variant, the NVAX+, primarily differed in its bus interface and external cache design, enabling it to operate on the same bus as the DECchip 21064, thus allowing seamless replacement.
Introduced in 1991, the NVAX series was incorporated into later VAX models such as the MicroVAX 3100, VAXstation 4000, VAX 4000, VAX 6000, VAX 7000/10000, and VAXft. Although it received updates throughout the early 1990s, the NVAX was ultimately replaced by the Alpha architecture featuring the DECchip 21064 in 1992.
The NVAX processors operated at clock frequencies ranging from 62.5 MHz (16 ns) up to 83.3 MHz (12 ns), while the NVAX+ ran at 90.9 MHz (11 ns). Performance benchmarks placed the NVAX around 25 VAX Unit of Performance (VUPs), with the NVAX+ achieving approximately 35 VUPs—nearing the ~40 VUPs delivered by the VAX 9000 mainframe but in a desktop-sized configuration.
The concluding iteration, known as the NVAX++ or NV5, achieved 50 VUPs and represented DEC's final processor for the VAX line before their full migration to the DEC Alpha platform.
Description
The NVAX microprocessor integrates approximately 1.3 million transistors on a die measuring 16.2 by 14.6 mm (236.52 mm²), manufactured using Digital’s fourth-generation CMOS-4 process (0.75 μm) with three layers of aluminum interconnects. Encased in a 339-pin pin grid array package, it supports clock speeds between 62.5 MHz and 83.3 MHz, delivering around 25 VUPs.
The NVAX+ maintained the core processor architecture but introduced a distinct bus interface and external cache system housed in a larger 431-pin array compatible with that of the Alpha processor. This design facilitated CPU upgrades without requiring modifications to existing systems and enhanced performance to roughly 35 VUPs, approaching that of high-end VAX 9000 mainframes.
Released in 1994, the NVAX++ (also called NV5) powered VAX 7000 Model 7x0 and VAX 10000 Model 7x0 systems at a clock rate of 133 MHz (7.5 ns). It was fabricated utilizing Digital’s fifth-generation CMOS-5 process (0.50 μm), boosting performance to approximately 50 VUPs. A higher-frequency variant running at 170.9 MHz was later introduced in the VAX 7000/10000 Model 8x0 in 1996.
Microarchitecture
The architecture of the NVAX is segmented into five semi-independent units: I-box, E-box, F-box, M-box, and C-box. It employs a macropipelined structure that enables simultaneous processing of multiple VAX macroinstructions through these autonomous units, each equipped with its own micropipeline.
The I-box is responsible for fetching and decoding VAX instructions and includes a direct-mapped virtual instruction cache (VIC) of 2 KB alongside a branch history table containing 512 entries. Its design aims to retrieve eight bytes of instruction data from the VIC every cycle.
The E-box manages execution of most integer instructions excluding floating-point operations and operates under microcode stored in a control store holding 1,600 words, with an additional capacity for patching up to 20 words.
Floating-point instructions and multiplication of 32-bit integers are handled by the F-box, which features a four-stage pipeline for these tasks along with a non-pipelined floating-point divider unit.