POWER2
| Industry | Computer hardware |
|---|---|
| Founded | June 16, 1911 in Endicott, New York, United States |
| Products | Microprocessors, including POWER2 |
| Website | www |
The POWER2, originally designated as RIOS2, is a microprocessor created by IBM that implements the POWER instruction set. It was introduced in September 1993 as the successor to the POWER1 and was integrated into IBM's RS/6000 platforms. Upon its debut, the POWER2 held the title of the fastest microprocessor, surpassing the Alpha 21064. Nevertheless, this advantage was overtaken later in 1993 by the Alpha 21064A. IBM documented that a POWER2 running at 62.5 MHz achieved scores of 73.3 on SPECint92 and 134.6 on SPECfp92 benchmarks.
Support for both POWER1 (RIOS) and POWER2 (RIOS2) architectures was discontinued in the open source GCC compiler starting with version 4.5.
Description
Relative to the POWER1, the POWER2 incorporated significant improvements to the POWER ISA, adding new instructions for both user and system-level operations. It operated at increased clock frequencies ranging from 55 to 71.5 MHz and included an extra fixed-point unit alongside an additional floating-point unit. The processor also featured an expanded instruction cache of 32 KB and data caches enlarged to either 128 or 256 KB. Its multi-chip structure consisted of six or eight semi-custom ICs depending on cache configuration, maintaining a similar division as POWER1 among units such as instruction cache, fixed-point, floating-point, storage control, and two or four data cache modules.
The eight-chip version contained approximately 23 million transistors spread over a total die area of 1,215 mm2. IBM manufactured these chips using a 0.72 μm CMOS technology with an effective channel length of 0.45 μm, incorporating one polysilicon layer and four metal interconnect layers. These components were assembled into a ceramic multi-chip module (MCM) that measured 64 mm by 64 mm.
POWER2+
Launched in May 1994, the POWER2+ was an enhanced iteration of the POWER2 tailored for transaction processing workloads by integrating an off-package L2 cache available in sizes of 512 KB, 1 MB, or 2 MB using standard burst SRAM technology. This cache connected through either a 64-bit or 128-bit bus depending on system class and employed a direct-mapped design with a line size of 128 bytes and a write-through caching policy. Cache tags were managed on the storage control unit chip. To accommodate smaller chip dimensions, the POWER2+ featured narrower memory buses (64 or 128 bits) and reduced data cache sizes (64 or 128 KB). Cost reduction was achieved by utilizing solder ball connect (SBC) packaging for the six-chip variant instead of an MCM.
POWER2 Super Chip (P2SC)
The POWER2 Super Chip (P2SC), released in October 1996, integrated the functionality of the original eight-chip POWER2 into a single die measuring 335 mm2 and containing about 15 million transistors. This chip was fabricated with IBM’s advanced 0.29 μm CMOS-6S process technology. Initial versions operated at clock speeds of either 120 or 135 MHz—nearly twice as fast as the original POWER2’s top frequency of 71.5 MHz—with memory and I/O buses running at half that speed. IBM reported benchmark results of 5.5 SPECint95_base and 14.5 SPECfp95_base for these models. A subsequent faster model running at 160 MHz was introduced in October 1997 using a refined 0.25 μm CMOS-6S2 process.
To accommodate integration onto a single chip, the P2SC scaled down its L1 data cache to 128 KB and reduced the data translation lookaside buffer (TLB) entries to 256 while eliminating an infrequently used TLB locking capability.
The P2SC was succeeded by the POWER3 processor in 1998 as IBM’s premier CPU for RS/6000 systems. Notably, it powered the IBM Deep Blue supercomputer that famously defeated world champion Garry Kasparov in their historic match in 1997, although Deep Blue’s chess-playing strength primarily stemmed from specialized VLSI expert system chips rather than from its P2SC processors themselves.
See also
References
- Ball, Richard (15 October 1997). "Chipville USA". Electronics Weekly.
- DeTar, Jim (22 August 1994). "IBM unveils Power2+; DEC introduces new Alpha AXP". Electronic News.
- Gwennap, Linley (4 October 1993). "IBM Reclaims Performance Crown with Power2". Microprocessor Report.
- Gwennap, Linley (26 August 1996). "IBM Integrates POWER2 into a Single Chip". Microprocessor Report.
- Lineback, J. Robert (28 June 1993). "IBM Prepares RISC Successor for Unix". Electronic News.
- Shippy, David (9 August 1994). "Overview of the Power2+ Processor". Hot Chips 6.
- Statt, Paul (January 1994). "Power2 Holds the Performance Lead—Temporarily". Byte.
Further reading
- — Chapter 6 provides an in-depth explanation of the POWER2 architecture and its processor