Alpha 21164
| Industry | Computer hardware |
|---|---|
| Founded | November 7, 1957 |
| Fate | Acquired by Compaq (1998) |
| Headquarters | Maynard, Massachusetts , United States |
The Alpha 21164, internally designated as EV5, is a microprocessor engineered by Digital Equipment Corporation that implements the Alpha instruction set architecture (ISA). Launched in January 1995, it succeeded the Alpha 21064A as Digital's premier CPU and was eventually succeeded by the Alpha 21264 in 1998.
History
The initial silicon fabrication occurred in February 1994, successfully booting operating systems such as OpenVMS, Digital UNIX, and Windows NT. Samples were distributed in late 1994, with the first commercial release at 266 MHz arriving in January 1995, followed by a 300 MHz variant in March. The final iteration running at 333 MHz was unveiled in October 1995. The Alpha 21164A, introducing a 400 MHz version, became Digital's flagship processor in 1996.
Users
Digital incorporated the Alpha 21164 into its lineup of AlphaServer servers and AlphaStation workstations, as well as within Alpha VME 5/352 and 5/480 single board computers and AlphaPC 164 series motherboards. The chip was also adopted by partner Cray Research, who integrated the 300 MHz version into their T3E-600 supercomputer. Additionally, third-party manufacturers like DeskStation developed workstations powered by the Alpha 21164.
Performance
Until Intel introduced the Pentium Pro in November 1995, the 21164 outperformed the earlier 275 MHz Alpha 21064A. A 200 MHz Pentium Pro surpassed the 300 MHz 21164 on the SPECint95_base benchmark; however, the Alpha maintained an advantage in floating-point operations. The subsequent 333 MHz model exceeded Pentium Pro performance but was later overtaken within the same year by processors such as the MIPS Technologies R10000 and Hewlett-Packard's PA-8000.
Description
The Alpha 21164 is a four-issue superscalar CPU capable of dispatching up to four instructions per clock cycle across four execution units: two dedicated to integer operations and two for floating-point tasks. Its integer pipeline consists of seven stages, while the floating-point pipeline extends to ten stages. The processor supports a virtual address space of 43 bits (8 TB) and a physical address space of 40 bits (1 TB).
Integer unit
The integer execution unit comprises two pipelines—the add pipeline and multiply pipeline—each optimized for specific instruction categories but both capable of processing common instructions such as add, logical operations, load, compare, and conditional move. The multiply pipeline is responsible for shift, store, and multiply instructions (utilizing a non-pipelined multiplier), whereas branch instructions are handled by the add pipeline.
Most integer instructions complete by stage five with one-cycle latency, except for branch and conditional move instructions which finalize in stage six to synchronize with dependent compare results.
The integer register file holds forty 64-bit registers: thirty-two conforming to the Alpha Architecture specification and eight reserved for use as a scratchpad by PALcode. It provides four read ports and two write ports evenly split between the two pipelines.
Floating-point unit
The floating-point unit contains two pipelines along with its own register file. One pipeline executes all floating-point instructions except multiplication, which is exclusively managed by the other pipeline. Both pipelines have four stages each. A non-pipelined divider linked to the add pipeline handles division operations with variable latency depending on precision: single-precision divides require between 15 and 31 cycles, while double-precision divisions take from 22 up to 60 cycles. Other floating-point instructions exhibit a consistent four-cycle latency.
Cache
The 21164 processor featured a three-tier cache hierarchy—two levels integrated on the chip and one optional external cache—totaling 7.2 million transistors.
At the first level, the cache was divided into an 8 KB instruction cache (I-cache) and an 8 KB data cache (D-cache), both direct-mapped with 32-byte cache lines. To boost efficiency, the dual-ported D-cache maintained duplicated storage and implemented a write-through strategy combined with allocation upon reads.
The on-chip secondary cache (S-cache) provided a sizable 96 KB to satisfy the processor's demand for bandwidth beyond what external caches could deliver. This cache was three-way set associative, designed with pipelining to enhance throughput, and required two cycles to access due to its capacity. Physically, it was split into two sections flanking critical execution units, enabling data to be returned within two cycles.
An optional third-level cache (B-cache) utilized external SRAM chips ranging from 1 MB up to 64 MB; however, smaller configurations offered limited benefit given the presence of the S-cache. This cache employed a direct-mapped layout with a write-back policy and allocation on writes. Unlike its predecessor that needed an external controller, the B-cache was managed by on-chip interface logic and supported both asynchronous and synchronous SRAMs, connecting through the system bus.
External interface
The external interface consisted of a 128-bit wide system bus operating at frequencies between 20 and 100 MHz, running at a rate 3 to 15 times slower than the internal clock speed (which could reach up to 300 MHz). The microprocessor itself generated the clock signal for this system bus.
Clock
The internal clock frequency was derived by halving an external clock input; thus, achieving a 300 MHz internal clock required supplying a 600 MHz external clock signal.
Fabrication
Containing 9.3 million transistors on a die measuring 299 mm² (16.5 mm by 18.1 mm), the Alpha 21164 approached the limits of its manufacturing process. It was produced using Digital’s fifth-generation CMOS-5 technology—a 0.50 µm CMOS process featuring four layers of aluminum interconnects. The chip operated at a voltage of 3.3 V, dissipating power ranging from 46 W at 266 MHz up to 56 W at 333 MHz.
Package
The processor came in a ceramic interstitial pin grid array (IPGA) package with 499 pins, sized at 57.40 mm square. It included a heat spreader equipped with two mounting studs designed for attaching a heat sink.
Alpha 21164 (EV56)
The Alpha 21164 was further developed into the EV56 (initially called Alpha 21164A), which ran at clock speeds between 366 MHz and 666 MHz.
History
Unveiled in October 1995, the EV56 entered sampling later that year, with initial products operating at 366 MHz released in 1996. By July of that year, Digital offered a 433 MHz variant priced at $1,492 per unit for orders exceeding one thousand units; meanwhile, a 500 MHz version was being sampled with volume shipments anticipated by September. The 600 MHz model reached mass production by March 1997. In June 1996, Samsung Electronics joined forces with Digital as a second source for EV56 production and exclusively manufactured the highest-speed variant running at 666 MHz. Manufacturing took place at Digital’s Hudson facility in Massachusetts as well as Samsung’s Kihueng plant in South Korea.
Prominent users included Cray Research, Digital itself, NetApp, and DeskStation. Cray implemented the EV56 processor at frequencies from 450 to 675 MHz within its later T3E supercomputers. Digital incorporated it across multiple platforms such as AlphaServers, AlphaStations, Celebris XL workstations, and Digital Personal Workstations. NetApp deployed this CPU in storage solutions operating up to speeds of 600 MHz. DeskStation integrated the EV56 into its Raptor Reflex workstation line.
Overview
The Alpha 21164A's primary improvement was the integration of Byte Word Extensions (BWX), which enhanced byte and word-level access through the multiply pipeline. This processor contained 9.66 million transistors housed within a 209 mm2 die measuring 14.4 mm by 14.5 mm. Digital fabricated it using their sixth-generation CMOS-6 process at 0.35 μm with four layers of interconnects, while Samsung also produced a version employing a similar 0.35 μm technology derived from their early 1996 0.3 μm process. The chip operated at 3.3 volts, consuming between 31 watts at 366 MHz and 48.5 watts when running at 600 MHz.
Alpha 21164PC (PCA56)
Launched on March 17, 1997, the Alpha 21164PC (PCA56) was a cost-optimized variant of the 21164A, jointly developed and manufactured by Digital and Mitsubishi Electric Corporation. Production by Mitsubishi ended in mid-1998 due to adverse market conditions.
The processor ran at frequencies of 400, 466, and 533 MHz and achieved cost reductions by removing the S-cache, thus lowering transistor count and die size. To compensate, the instruction cache size was doubled from 8 KB to 16 KB. It supported B-cache configurations ranging from 512 KB up to 4 MB, with typical sizes being 1 or 2 MB. Incorporating Motion Video Instructions (MVI), a SIMD extension designed to boost MPEG encoding efficiency, it featured a virtual address space of 43 bits and a physical address space of 33 bits.
This model contained approximately 3.5 million transistors on a die measuring 141 mm2 (8.65 mm × 16.28 mm). Digital fabricated it using the CMOS-5 process and packaged it in a 413-pin IPGA with dimensions of 49.78 mm by 49.78 mm. Power consumption varied from 26.5 watts at 400 MHz to 35 watts at 533 MHz, operating at a voltage of 3.3 V.
Digital utilized the Alpha 21164PC within their AlphaPC 164SX motherboard lineup.
Alpha 21164PC (PCA57)
The PCA57, a derivative of the PCA56, was developed by Samsung Electronics and introduced in late 1998 using a refined 0.28 μm CMOS fabrication process. It operated at clock speeds of 533, 600, and 666 MHz and featured doubled cache sizes: a 32 KB instruction cache and a 16 KB data cache.
Containing around 5.7 million transistors on a compact die area of 101 mm2, this chip ran at a reduced voltage of 2.5 V and consumed between 18 and 23 watts depending on frequency.
Digital incorporated the PCA57 into its AlphaPC 164RX motherboard series.
Chipsets
Both Digital and VLSI Technology developed chipset solutions compatible with the Alpha 21164 family. Additionally, Digital engineered specialized ASICs tailored for high-performance AlphaServer systems such as the AlphaServer 8200 and AlphaServer 8400.
21171
The 21171 chipset, code-named Alcor, debuted in January 1995 alongside the original Alpha 21164 processor as Digital’s inaugural chipset for this CPU line. It represented an advancement over the DECchip 21071 by supporting the updated system bus protocol and consisted of one control chip integrating memory and PCI controllers plus four data slice chips that bridged a wide, 256-bit memory bus with a narrower, PCI bus running at a frequency of 33 MHz.
21172
Known as Alcor2, the 21172 chipset was an enhanced iteration designed to support the improved capabilities of the Alpha 21164A processor.
Pyxis
Targeted at budget-conscious systems, the Pyxis chipset (21174) supported both the Alpha 21164A and the Alpha 21164PC CPUs through an integrated single-chip solution housed in a ceramic ball grid array (CBGA) package with 474 contacts. This chipset found use in economical products like the Digital Personal Workstation a-Series as well as AlphaPC models such as the 164LX and164SX, retailing at approximately US$142 per unit in bulk quantities.
The Pyxis combined memory and PCI controllers on one chip, enabling support for up to half a gigabyte of ECC or parity-protected SDRAM via a wide,128-bit memory interface while providing PCI or PCI-X input/output functionality.
Polaris
Introduced by VLSI Technology in June 1997, Polaris is a system controller designed for personal computers that accommodates the 21164A and 21164PC processors. It supports memory configurations of up to 768 MB EDO DRAM or 512 MB SDRAM via a 128-bit wide memory bus and features a 32-bit PCI bus operating at 33 MHz.
Digital incorporated Polaris within its AlphaPC 164RX motherboard design.
Further reading
- Bannon, P. and Saito, Y. (1997). "The Alpha 21164PC microprocessor". Compcon '97 Proceedings, pages 20–27.
- Bhandarkar, Dileep P. (1995). Alpha Architecture and Implementations. Digital Press.
- Carlson, D. and colleagues (1998). "A 667 MHz RISC microprocessor featuring a 6.0 ns 64-bit integer multiplier". ISSCC Digest of Technical Papers, pages 294–295.
- Carlson, D.A.; Castelino, R.W.; Mueller, R.O. (November 1997). "Multimedia extensions for a 550-MHz RISC microprocessor". IEEE Journal of Solid-State Circuits 32 (11): pages 1618–1624.
- Jain, A.K. et al. (1997). "1.38 cm2 550 MHz microprocessor incorporating multimedia extensions". ISSCC Digest of Technical Papers, pages 174–175, 451.
- Gronowski, Paul E. et al. (May 1998). "Designing high-performance microprocessors". IEEE Journal of Solid-State Circuits 33 (5): pages 676–686.
- Kobayashi, S. and co-authors (1997). "A 550 MHz Alpha microprocessor aimed at PC applications". Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications, pages 203–207.