Alpha 21464

Alpha 21464
Company type	Microprocessor project
Industry	Semiconductor
Predecessor	Alpha 21364
Founded	Mid-1990s
Fate	Cancelled on 25 June 2001
Headquarters	United States
Products	Microprocessor implementing Alpha ISA

The Alpha 21464 represented an incomplete microprocessor project implementing the Alpha instruction set architecture originally created by Digital Equipment Corporation and subsequently managed by Compaq. Also referred to as EV8 with the codename Araña, its launch was scheduled for 2004 but was terminated on 25 June 2001 when Compaq chose to discontinue the Alpha line in favor of Itanium. At the time of cancellation, the processor was in advanced development stages but had not yet undergone taped out.

The concept emerged during the mid-1990s, influenced by computer scientist Joel Emer, who drew inspiration from Dean Tullsen's work on simultaneous multithreading (SMT) at the University of Washington. Emer championed SMT technology in the late 1990s, leading Compaq to announce in October 1999 that their forthcoming Alpha microprocessor would integrate SMT, with anticipated delivery in 2003.

Description

This microprocessor incorporated an eight-issue superscalar architecture featuring out-of-order execution, four-way SMT, and a deeply pipelined structure. It retrieved 16 instructions per cycle from a 64 KB two-way set-associative instruction cache. A branch predictor selected the best instructions for a collapsing buffer capable of handling up to 16 instructions per cycle, contingent on branch density. The front-end contained more pipeline stages than earlier Alpha models, resulting in a substantial minimum branch misprediction penalty of 14 cycles, which was alleviated by an advanced branch prediction mechanism.

Implementing SMT necessitated duplicating certain resources such as program counters—four were maintained for four threads—while only minimally increasing logic beyond the front-end. The register file held 512 entries sized according to the maximum number of in-flight instructions rather than SMT threads, requiring three pipeline stages for access due to its circuit complexity. Each cycle could dispatch up to eight instructions from four threads to eight integer units and four floating-point units. The 21464 also featured a 64 KB data cache arranged into eight banks with dual-port capability, supported by a 3 MB six-way set-associative unified secondary cache.

A distinctive innovation was the integer execution unit’s register cache, designed to streamline operand bypass handling by storing all results from ALU and Load pipelines over recent cycles. This structure was essentially an architectural redefinition of previously distributed multiplexers rather than a solution aimed at reducing register file latency.

The system interface shared similarities with that of the Alpha 21364, including integrated memory controllers managing ten RDRAM channels. Multiprocessing capabilities were enabled through a router connecting multiple 21464 processors, architecturally supporting up to 512-way multiprocessing without requiring additional glue logic.

Fabricated using a 0.125 μm CMOS process incorporating seven layers of copper interconnects, partially depleted silicon-on-insulator (PD-SOI), and low-K dielectric materials, the design targeted roughly 250 million transistors on a die measuring approximately 420 mm².

Tarantula

The codename Tarantula referred to an Alpha architecture extension derived from the Alpha 21464, intended to introduce vector processing functionality. This project was discontinued during development before implementation commenced and prior to the completion of the 21464 itself. The design planned for thirty-two vector registers each sized at 64 by 128 bits (1 KB), around fifty vector instructions, along with supplementary data movement commands. Other successors to EV8 under consideration included a multicore design featuring two EV8 cores operating at 4.0 GHz.

Description

Tarantula

Further reading