CDC 160 series
| Industry | Computer hardware |
|---|---|
| Founded | 1957 |
| Founder | William Norris, Seymour Cray |
| Headquarters | Minneapolis , United States |
| Products | CDC 160 series minicomputers |
The CDC 160 series consisted of minicomputers created by Control Data Corporation between 1960 and 1965. The CDC 160 and CDC 160-A models were built with a 12-bit architecture, whereas the CDC 160G utilized a 13-bit design while maintaining backward compatibility with the CDC 160-A instruction set. Conceived by Seymour Cray—allegedly developed within a single weekend—the CDC 160 was recognized as CDC’s inaugural $60,000 desk computer and functioned as an early prototype for I/O processing units in subsequent high-performance machines such as the CDC 6600 and 7600.
Its design incorporated ones' complement arithmetic with end-around carry, enabling efficient computation for its era. Approximately 400 units were produced and delivered. During the 1960s, the CDC 160-A was also marketed in partnership with National Cash Register (NCR), who sold it under their own label, thereby broadening its commercial distribution.
Overview
A publishing firm that purchased a CDC 160-A characterized it as "a single-user system without batch processing capabilities. Operators would enter the computer room, sit at the console, load the bootstrap from paper tape, and initiate a program."
The CDC 160-A offered a straightforward yet well-equipped environment, providing scaled-down versions of features found in larger machines. It was particularly suited for training beginner programmers on advanced topics such as low-level input/output (I/O) operations, virtual memory management, and interrupt handling.
Every system in the 160 series came standard with a paper-tape reader and punch, and most were outfitted with a modified IBM Electric typewriter used as a computer terminal. The memory capacity was 4,096 words of 12 bits each. The central processor included a 12-bit ones' complement accumulator but did not support multiplication or division instructions. Its instruction set featured various addressing modes, including indirect addressing that was nearly as functional as index registers, along with both relative and absolute addressing options. Initially, there was no dedicated subroutine call instruction, and only one memory bank could be accessed at a time.
The CDC 160-A introduced a "return jump" instruction to facilitate subroutine calls and implemented bank-switching to access additional memory banks of 4K words each, expanding total addressable memory up to 32,768 words. Due to size and expense, this extra memory was housed in a separate cabinet. Additionally, the 160-A could be equipped with an optional multiply/divide unit, which was another sizable peripheral device.
Memory cycle duration was 6.4 microseconds; executing an addition required two cycles. Average instruction execution time was roughly 15 microseconds, resulting in a throughput of about 67,000 instructions per second.
The CDC 160G upgraded the architecture by extending registers and memory word size to 13 bits—fully utilizing all bits in G mode while preserving binary compatibility with the 160-A in A mode. It also incorporated built-in multiply/divide instructions alongside new addressing modes.
Low-level I/O capabilities included device control signals, status monitoring, and data transfer either as single bytes or blocks. I/O operations could be directed to registers or memory locations or performed via direct memory access (DMA). Standard I/O operations would pause CPU activity until completion; however, DMA enabled simultaneous CPU instruction execution during data transfers. The interrupt system was fully based on I/O events, where external interrupts indicated occurrences such as DMA completion—an important concept for those learning programming fundamentals.
Application Domains
- Immediate processing tasks
- Batch data transformation
- Scientific computation
- Commercial information handling
- Data gathering and compression
- Engineering analysis and solutions
- Telemetry and communication networks
- Control Data's Satellite Computing System
Peripheral Devices
- Magnetic tape units 163 or 164
- Typewriter model 161
- Card reader and punch system 1610
- Line printer model 1612
- Plotter unit 165
- Buffered line printer 166
- Card reader device 167
- Arithmetic processing unit 168
- Auxiliary memory module 169
- Paper tape reader 350
- Teletype paper and tape punch BRPE-11 model
- Magnetic tape transporter 603
Follow-up Models
The architecture of the CDC 160 was utilized as the foundation for the peripheral processors (PPs) within the CDC 6000 series mainframe computers and their successors. A significant portion of the original 160 instruction set was preserved, with added capabilities to support data channel programming and central processor management in the 6000 series. Initially, nearly all of the operating system operations were executed on these PPs, which released the main processor to focus on user-level tasks, thereby enhancing overall system performance.
Related Topics
- IBM 1620, a desktop scientific computer launched by IBM in 1959
- CAB 500, a desktop scientific computer introduced by SEA in 1960