Jump to content

CDC 6000 series

From Alfawiki
Control Data Corporation
IndustryComputer hardware
Founded1957; 69 years ago (1957)
FounderWilliam Norris, Seymour Cray (chief designer of CDC 6000 series)
Headquarters
Minneapolis, Minnesota
,
United States
ProductsCDC 6000 series mainframe computers (CDC 6200, CDC 6300, CDC 6400, CDC 6500, CDC 6600, CDC 6700)

The CDC 6000 series represents a now-obsolete line of mainframe computers developed by Control Data Corporation during the 1960s. This lineup encompassed models like the CDC 6200, CDC 6300, CDC 6400, CDC 6500, CDC 6600, and CDC 6700. These substantial solid-state digital machines were engineered for both scientific computations and commercial data processing tasks. They supported advanced features such as multiprogramming, multiprocessing, Remote Job Entry, time-sharing, and comprehensive data management through the SCOPE operating system. By 1970, an additional time-sharing operating system called KRONOS became available. This series marked the advent of the first generation of supercomputers, with the CDC 6600 standing out as Control Data's premier offering.

Overview

The architecture of the CDC 6000 series is composed of four primary elements:

  • central memory
  • one or two high-speed central processing units
  • ten peripheral processors (referred to as Peripheral Processing Units, or PPUs)
  • a user interface console

This series employs a distributed system design.

The various models are distinguished primarily by the configuration and type of central processors:

  • CDC 6400: equipped with a single CPU featuring a unified arithmetic unit that processes instructions sequentially.
  • CDC 6500: a dual-CPU configuration consisting of two CDC 6400 processors.
  • CDC 6600: includes one CPU with ten parallel functional units capable of executing multiple instructions simultaneously.
  • CDC 6700: combines two CPUs—one modeled after the CDC 6600 and another based on the CDC 6400 architecture.

Certain characteristics and terminology trace back to the earlier CDC 3000 computers:

  • Use of ones complement arithmetic.
  • COMPASS: the assembly language employed across both series.
  • SCOPE: the operating system implemented on both the CDC 3000 and CDC 6000 series.

As of 2018, only one CDC 6000 series system remains operational—a restored CDC 6500 built in 1967. Initially utilized by Purdue University until 1989, it was then preserved at the Chippewa Falls Museum of Industry and Technology before being acquired by Paul Allen for display at the Living Computers: Museum + Labs.

History

The inaugural model in the CDC 6000 series was the CDC 6600, engineered by Seymour Cray and James E. Thornton in Chippewa Falls, Wisconsin. Released in September 1964, it achieved a performance rate of up to three million instructions per second—tripling the speed of IBM’s Stretch, which was then considered the fastest machine. The CDC 6600 held this top position for five years until superseded by the CDC 7600. It utilized Freon-based cooling and was priced between $6 million and $10 million per unit, with approximately one hundred systems produced.

Subsequently, in April 1966, Control Data introduced the CDC 6400, a more economical and slower alternative that processed instructions serially rather than employing parallel functional units like the CDC 6600; otherwise, it shared much of its design. In October 1967, Control Data launched the CDC 6500, a dual-processor system comprising two CPUs similar to those in the CDC 6400, primarily designed by Thornton. The CDC 6700, combining a CPU from the CDC 6600 with another from the CDC 6400, appeared in October 1969.

The series was further extended through specialized variants including:

  • A secondary configuration lacking a Central Processor (model numbers beginning with 6416), functioning as an "Augmented I/O Buffer and Control" unit to facilitate additional peripheral devices and improve multiprogramming alongside batch processing capabilities.
  • Versions of the CDC 6400 outfitted with fewer peripheral processors:
    • CDC 6415–7 equipped with seven peripheral processors
    • CDC 6415–8 equipped with eight peripheral processors
    • CDC 6415–9 equipped with nine peripheral processors

Central memory (CM)

Within the CDC 6000 series, the central processor oversees approximately seven concurrent programs (jobs) residing in central memory. Instructions are fetched into processor registers, executed, and their outcomes stored back into memory. Each word in central memory consists of 60 bits, supported by optimized mechanisms that allow word transfers in as fast as 100 nanoseconds.

Extended Core Storage (ECS)

Extended Core Storage (ECS) expands the system’s memory capacity and boosts processing capabilities. It is composed of interleaved core banks, each 488 bits wide and equipped with a buffer for every bank. Although ECS generally operates at a slower pace compared to CM, its buffering capabilities can sometimes provide superior performance depending on the workload characteristics.

Central processor

Exchange Jump Package
P A0 B0 = 0
RA (CM) A1 B1
FL (CM) A2 B2
EM A3 B3
RA (ECS) A4 B4
FL (ECS) A5 B5
A6 B6
A7 B7
X0
X1
X2
X3
X4
X5
X6
X7

Legend:

  • P: Program Address (18 bits)
  • RA: Reference Address
  • FL: Field Length
  • CM: Central Memory (18 bits)
  • ECS: Extended Core Storage (24 bits)
  • EM: Exit Mode (18 bits)
  • A0-A7: Address registers (18 bits)
  • B1-B7: Increment registers (18 bits)
  • X0-X7: Operand registers (60 bits)

The central processor functions as a rapid arithmetic unit responsible for executing operations such as addition, subtraction, logical processing, multiplication, division, indexing, and branching within user programs. Importantly, it does not perform input/output (I/O) tasks; instead, I/O operations are handled asynchronously by dedicated peripheral processors.

Each CPU is outfitted with 24 registers: eight 60-bit X registers used for data operations; eight 18-bit B registers primarily serving indexing and addressing functions (with B0 fixed at zero and B1 commonly set to one); and eight 18-bit A registers paired with X registers for loading from and storing to memory. Registers A0 and X0 act as scratch registers and are utilized during ECS addressing.

Instructions vary in length from 15 to 30 bits, allowing up to four instructions per 60-bit word. Opcodes occupy six bits; instructions may operate between registers or include immediate values. For instance, COMPASS assembly code efficiently loads data from memory, performs addition, and stores results.

The CDC 6400 CPU employs a unified arithmetic section executing one instruction at a time with operation latencies ranging from five to 68 clock cycles depending on instruction type. The CDC 6500 contains two such CPUs, effectively nearly doubling processing capacity while sharing I/O channels.

In contrast, the CDC 6600 enhances performance by partitioning its central processor into ten specialized functional units—covering branch, Boolean logic, shift operations, long integer addition, two floating-point add/divide/multiply units, and two increment units—enabling parallel execution of instructions. Latencies span from three to 29 clock cycles. An instruction issue rate of one per clock cycle is sustained through a scoreboard system and an instruction stack capable of holding eight instruction words.

Both the CDC 6400 and CDC 6600 operate with a cycle time of 100 nanoseconds (10 MHz). The CDC 6400 delivers roughly 1 MIPS with floating-point operations below 200 kFLOPS due to slower multiplication speeds. Meanwhile, the CDC 6600 achieves peak rates near 10 MIPS with floating-point additions completed in four cycles and multiplications in ten cycles across two multiplier units, resulting in peak floating-point performance between 2 and 3 MFLOPS.

The CDC 6700 integrates characteristics from both the CDC 6500 and CDC 6600 models by featuring two central processors—one with a unified arithmetic section CPU and another with multiple functional units—making it the most powerful and fastest machine within the CDC 6000 series.

Architecture of CDC 6000 series
Model I/O Channels Peripheral Processors Central Memory Central Processor
Registers Functional Units
CDC 6400 12 10 1 24 Unified Arithmetic Section
CDC 6500 12 10 1 24 Unified Arithmetic Section
24 Unified Arithmetic Section
CDC 6600 12 10 1 24 Add, Multiply (2x), Divide, Long add, Shift, Boolean, Increment (2x), Branch
CDC 6700 12 10 1 24 Unified Arithmetic Section
24 Add, Multiply (2x), Divide, Long add, Shift, Boolean, Increment (2x), Branch

Peripheral processors

The central processing unit shares access to the main memory with up to ten peripheral processors (PPs), each equipped with a 1 μs memory consisting of 4K 12-bit words. These PPs are similar in design to CDC 160A minicomputers, matching the 12-bit word size and incorporating elements of the same instruction set.

Primarily intended to handle the 12 I/O channels, these peripheral processors execute parts of the Chippewa Operating System (COS) and its variants such as SCOPE, MACE, KRONOS, NOS, and NOS/BE. Only PPs have direct access to these channels and are responsible for managing input/output operations between central memory and external devices like disks and magnetic tape units. By delegating I/O functions to PPs, the central processor is freed to concentrate on computational tasks, thereby improving overall system efficiency. A significant portion of the operating system runs on these peripheral processors, ensuring that the central processor remains available primarily for executing user applications.

Each PP is capable of performing arithmetic operations such as addition and subtraction, logical operations, and specialized instructions that facilitate data transfers between its own memory and connected peripherals at speeds up to 1 μs per word. The group of PPs operates collectively as a barrel processor, sharing hardware resources while maintaining separate registers and memory modules. Each processor executes its routines independently, serving as an early form of bus mastering or direct memory access.

Instructions consist of a six-bit opcode along with six bits allocated for operands; when combined with the subsequent word’s 12 bits, this yields an 18-bit address space capable of addressing all 131,072 words of Central Memory.

Data channels

Peripheral processors interface with devices through data channels—dedicated communication pathways linking one device per channel. Hardware modifications can enable a channel to support multiple devices. These data channels do not directly access either central or peripheral memory; instead, they depend on programs running on peripheral processors to control memory access or sequence chained operations.

At any given moment, only one peripheral processor may use a particular data channel to communicate with its associated device; however, it is possible for one peripheral processor to write data into a channel while another reads from it simultaneously.

Display console

Interaction between the computer operator and the operating system occurs via the computer console, which features two CRT displays. This setup represented a significant advancement compared to contemporary consoles that relied heavily on numerous blinking lights and switches to indicate machine status. The CDC 6000 series console provided a more straightforward, faster, and dependable user interface.

The console utilizes calligraphic display technology driven by analog circuitry that directs electron beams to render characters on screen. A peripheral processor runs a specialized program named "DSD" (Dynamic System Display), which continuously refreshes the display to eliminate flicker.

DSD shows system status updates and job-related information, while the console’s keyboard enables operators to modify programs and retrieve job data. In 1967, this console introduced O26, a full-screen text editor among the earliest available; however, CDC postponed making full-screen editors widely accessible for time-sharing environments by about fifteen years.

Furthermore, several games were developed specifically for the operator console, including BAT (a baseball game), KAL (a kaleidoscope simulation), DOG (featuring Snoopy piloting his doghouse), ADC (an Andy Capp animation), EYE (animated eyeballs), PAC (a Pac-Man style game), and a lunar lander simulation.

Minimum system requirements

A CDC 6000 series setup necessitates a central processor equipped with 32,768 words of memory, supplemented by storage devices like disks, disk packs, or drums with a combined capacity of 24 million characters. Essential peripherals consist of a punched card reader and punch, a printer with its controllers, and two seven-track magnetic tape drives.

For more extensive configurations, options included expanded central memory up to 131,072 words, extended core storage (ECS), additional disk or drum units, extra card readers and punches, printers, tape drives, graphic plotters, and microfilm recorders to accommodate various business applications.

Peripheral equipment

  • CDC 405 Card Reader – Capable of processing 80-column cards at a rate of 1200 cards per minute and 51-column cards at 1600 cards per minute. Each tray can hold up to 4000 cards to reduce the frequency of reloading.
  • CDC 6602/6612 Console Display
  • CDC 6603 Disk System
  • CDC 606 Magnetic Tape Drives (7-track, IBM-compatible)
  • CDC 626 Magnetic Tape Drives (14-track)
  • CDC 6671 Communications Multiplexer – Supports up to 16 synchronous data lines at 4800 bits per second for Remote Job Entry
  • CDC 6676 Communications Multiplexer – Handles up to 64 asynchronous data lines at 300 bits per second for timesharing access
  • CDC 6682/6683 Satellite Coupler
  • CDC 6681 Data Channel Converter

Model variants

The CDC 6600 stood as the premier model. The CDC 6400 was a slower and less powerful CPU offered at a substantially reduced price.

The CDC 6500 incorporated two 6400 CPUs but only one set of I/O peripheral processors (PPUs), targeting workloads dominated by computation. Meanwhile, the CDC 6700 combined a single 6600 CPU with one 6400 CPU in a dual-processor arrangement. The CDC 6415 was an even more economical and slower version featuring fewer PPUs (seven to nine instead of ten). The CDC 6416 upgrade added an additional PPU bank to any machine in the 6000 series, raising the total PPUs to twenty and channels to twenty-four, thereby improving input/output throughput.

The CDC 6600

The CDC 6600 served as Control Data Corporation’s flagship supercomputer within the 6000 series. Recognized as the first truly successful supercomputer, it delivered performance three times greater than its predecessor, the IBM 7030 Stretch. With speeds reaching up to three megaFLOPS, approximately one hundred units were sold. It held the title of the fastest computer worldwide from its debut in 1964 until it was surpassed by the CDC 7600 in 1969.

The architecture of the CDC 6600 anticipated principles later associated with RISC designs and uniquely utilized ones'-complement for integer representation. Its architectural innovations influenced computer designs for over thirty years. Notably, it was the first widely adopted system featuring a load–store architecture where writes to address registers triggered memory operations on data registers.

Initial installations in 1965 included prominent research centers such as Livermore and Los Alamos National Laboratories, NYU’s Courant Institute, and CERN near Geneva—which employed it to process millions of bubble-chamber images annually. Additional systems were deployed for nuclear event analysis at Lawrence Radiation Laboratory and academic research at the University of Texas at Austin.

A preserved CDC 6600 is on display at the Computer History Museum located in Mountain View, California.

The 6400

The CDC 6400, a member of Control Data Corporation's 6000 series from the 1960s, is a mainframe computer designed to be architecturally consistent with the CDC 6600. In contrast to the 6600, which incorporated 10 parallel functional units enabling concurrent instruction execution, the 6400 utilized a single, consolidated arithmetic unit that processed one instruction sequentially. This architectural choice led to reduced computational speed but offered significant cost savings. Aside from this difference, its memory system, peripheral processor-driven input/output (I/O), and peripheral devices were essentially the same as those found in the 6600.

In December 1966, a CDC 6400 was installed at UC Berkeley for academic computing purposes and remained operational until August 1982. The system also represented a significant advancement in Europe when RWTH Aachen University acquired a CDC 6400 in 1966, becoming Germany’s first and Europe’s second Control Data supercomputer following CERN. This installation supported the entire university through 64 remote teletypes until it was superseded by a CDC Cyber 175 in 1976.

The 6500

The CDC 6500, which combined two 6400 CPUs, stands as the third supercomputer model in Control Data Corporation's 6000 series, engineered by supercomputing pioneer Seymour Cray. Announced in 1964 and released in 1967, the system integrates twelve autonomous computers: ten peripheral and control processors each with their own memory, operating independently from the pair of central 6400 CPUs. Unlike its predecessors, it featured a liquid cooling system with dedicated refrigeration units assigned to each of its three bays.

Notable installations of the CDC 6500 included:

The 6700

The CDC 6700 combined both a CDC 6600 and a CDC 6400 into one system, representing the highest-performance model within the CDC 6000 series.

See also

  • CDC Cyber – successors to the Control Data Corporation’s 6000 series machines

References

  1. CONTROL DATA 6400/6500/6600 Computer Systems Reference Manual, Publication No. 60100000 D, 1967
  2. CONTROL DATA 6400/6500/6600/6700 Computer Systems, SCOPE 3.3 User's Guide, Publication No. 60252700 A, 1970
  3. CONTROL DATA 6400/6500/6600/6700 Computer Systems, SCOPE Reference Manual, Publication No. 60305200, 1971
  4. Computer history on CDC 6600
  5. Gordon Bell on CDC computers

External links

Retrieved from "https://www.alfawiki.org/index.php?title=CDC_6000_series&oldid=25177"