CDC 7600
| Industry | Computer hardware, Supercomputing |
|---|---|
| Founded | 1957 |
| Founder | William Norris |
| Headquarters | Minneapolis , United States |
| Products | CDC 6600, CDC 7600, CDC 8600, CDC STAR-100 |
| Website | www |
The CDC 7600, created by Seymour Cray as the follow-up to the CDC 6600, solidified Control Data Corporation's dominance in the supercomputing field during the late 1960s and early 1970s. Running at 36.4 MHz and equipped with a primary magnetic core memory of 65 Kwords alongside up to 512 Kwords of secondary memory, it delivered performance approximately ten times greater than its predecessor. The machine reached around 10 MFLOPS on carefully optimized programs, with peak speeds hitting 36 MFLOPS.
Benchmark comparisons conducted circa 1970 demonstrated that the CDC 7600 surpassed its chief rival, the IBM System/360, Model 195. Initially, base models were priced near $5 million, with expenses rising as additional options were included.
One of its notable design breakthroughs was the unique C-shaped chassis, which reduced the amount of floor space required and enhanced performance by shortening signal path lengths. This design choice also complemented its sophisticated instruction pipelining mechanism.
Design
As production of the 6600 neared completion, Cray redirected his efforts toward developing its successor, targeting a tenfold improvement in speed. Although advances like integrated circuits and faster transistors yielded incremental speed enhancements, Cray aimed for a far more substantial leap beyond the common two- to fivefold gains.
The original 6600 achieved high speed by employing multiple functional units working concurrently, enabling simultaneous execution of operations such as addition and multiplication. However, each functional unit had to finish processing one instruction before accepting another, which caused bottlenecks when the instruction scheduler exhausted available instructions. Simply increasing the number of functional units would not resolve this limitation without a scheduler capable of managing more parallel instructions.
To overcome this challenge, Cray introduced an instruction pipeline that segmented functional units into consecutive stages—like operand fetching, computation, and result storage—that overlapped in execution time. This approach allowed new instructions to enter the pipeline before previous ones completed, greatly boosting throughput. For instance, while the multiply unit on the 6600 required 10 cycles per instruction, pipelining aimed to multiply its effective speed accordingly.
Although achieving flawless pipelining is difficult due to hardware limitations, the CDC 7600 managed roughly triple the performance of the 6600 through this technique. Additional improvements stemmed from faster transistor technology and compact circuit modules composed of six tightly stacked printed circuit boards packed with resistors, diodes, and transistors. This dense assembly increased operational speed but made module repairs more complex.
The condensed layout generated considerable heat; therefore, Cray enlisted refrigeration specialist Dean Roush (formerly at Amana) to attach aluminum cooling plates to the rear of each cordwood module stack. These plates were cooled via a liquid freon system circulating through the machine’s core. Since mechanical cooling systems can fail, the machine’s large "C" configuration allowed technicians to access components located inside the curve for maintenance without dismantling cooling infrastructure.
Architecture
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The CDC 7600 represented a significant architectural advancement by employing a load-store architecture with a streamlined instruction word length of just 15 bits and utilizing only 64 machine codes—excluding fixed-point multiply or divide instructions within its central processor.
It featured two types of core memory: a small core memory designed for active instructions and data access with a rapid cycle time of 10 minor cycles at 27.5 nanoseconds each and a word size of 60 bits, alongside a larger core memory intended for data transfer that operated at a slower pace of 60 minor cycles per access with words sized at 480 bits (512 including parity). Both memories functioned concurrently using pipelined buffered accesses, facilitating sequential transfers of 60 bits every 27.5 nanoseconds between them. The operating system managed data movement between these memories by swapping contents as needed for efficient processing.
The system incorporated a twelve-word instruction pipeline known as an "instruction word stack," prefetching all relevant addresses to optimize execution flow during conditional branches and loops. Within loops comprising up to forty instructions, necessary instructions remained resident in this stack, reducing fetch operations and freeing small core memory capacity for data storage.
Arithmetic and logic operations utilized eight operand registers of sixty bits each, each paired with an address register. Transferring an address into an address register triggered read or write operations in small core memory. Although processor wait states could occur if data or floating-point units were not immediately ready, pipelining effectively minimized such delays.
Relationship with the CDC 6600
The CDC 7600 was engineered to maintain machine code compatibility with the CDC 6600, aiming to provide a significant increase in processing speed. Users observed that the majority of software could operate on either machine without requiring alterations. While both systems shared numerous characteristics—including hardware components, instruction formats, and a 60-bit word length—the 7600 did not support object-code compatibility with the 6600. Additionally, full source-code compatibility using COMPASS was not achieved due to variations in their instruction sets. Originally designated as the CDC 6800, the system was renamed the 7600 after Cray recognized that complete compatibility could not be guaranteed. Nevertheless, their operating systems offered a consistent software environment that simplified software migration between the two platforms.
Both models utilized block-structured memory featuring independent access channels. Cray's design innovation involved delegating routine operations such as input/output to ten smaller 12-bit Peripheral Processor Units (PPUs), thereby freeing the central CPU to concentrate solely on computation tasks. These PPUs controlled data transfers and peripheral devices, ensuring that the CPU’s memory remained current while minimizing latency. This architectural choice enhanced mathematical processing efficiency by offloading administrative duties.
The 7600 employed 60-bit words containing mostly 15-bit instructions, with some instructions extending to 30 bits, all packed within these words. Its instruction set was adapted to accommodate new memory configurations, which resulted in incompatibility with the 6600 but facilitated easier porting of compilers and operating systems. Early users frequently developed custom operating systems—such as LTSS and NCAROS—and compilers like LRLTRAN, a Livermore-specific Fortran variant incorporating dynamic memory management.
CDC also introduced the CDC 7700, a multiprocessor system composed of two interconnected 7600 units arranged asymmetrically as central and adjunct processors. This configuration was utilized for missile launch detection and tracking incoming Soviet ICBMs, incorporating real-time radar simulation supported by a CDC 6400 I/O front-end. Deployments included TRW in Redondo Beach (later moved to Kwajalein Atoll) and McDonnell Douglas in Huntington Beach, California; these sites linked their systems via chassis 25 to operate as a unified multiprocessor setup.
Reception and usage
Between 1969 and 1975, the CDC 7600 was widely acknowledged as the fastest general-purpose computer worldwide, excluding specialized machines. Despite its innovative design and cooling systems, it suffered from frequent operational failures; institutions such as LLNL and NCAR reported breakdowns occurring daily, sometimes reaching up to five incidents per day. Resolving these reliability issues at installation locations often took several years. Although it achieved moderate sales within its high-performance segment, the CDC 7600 likely did not produce substantial profits for Control Data Corporation. Its intended successor, the CDC 8600, was never finalized, prompting Seymour Cray to found Cray Research.
A CDC 7600 is partially preserved at the Computer History Museum, where only two corner modules are exhibited due to its large size; the remainder of the system is kept in storage. Another example is displayed at the Chippewa Falls Museum of Industry and Technology, accompanied by its console and tape controller.
External links
- Neil R. Lincoln alongside 18 engineers from Control Data Corporation (CDC) discussing computer architecture and system design, Charles Babbage Institute, University of Minnesota. Topics cover CDC 1604, CDC 6600, CDC 7600, CDC 8600, CDC STAR-100 and Seymour Cray.
- Presentation on the CDC 7600 and additional Seymour Cray projects by C. Gordon Bell at Microsoft Research.
- SCD Computer Gallery
- Computer History Museum
- Chippewa Falls Museum of Industry and Technology
- Archive of CDC 7600 materials
