CDC 6600
| Industry | Computer hardware |
|---|---|
| Founded | January 1, 1957 |
| Founder | William Norris |
| Headquarters | Minneapolis , United States |
| Products | CDC 6000 series mainframe computers, including CDC 6600 supercomputer |
The CDC 6600 stood as the premier model within the CDC 6000 series of mainframe computers produced by Control Data Corporation. Engineered by Seymour Cray, it is widely recognized as the first truly successful supercomputer, surpassing its forerunner, the IBM 7030 Stretch, by nearly a factor of three. Achieving speeds up to three megaFLOPS, it held the title of the fastest computer globally from its launch in 1964 until 1969, when it was succeeded by the CDC 7600.
Deliveries commenced in 1965, primarily to prominent government research centers such as Lawrence Livermore National Laboratory and Los Alamos National Laboratory. The machine rapidly became indispensable for advanced scientific and mathematical computations, with installations at institutions including the Courant Institute of Mathematical Sciences, CERN, and Lawrence Berkeley National Laboratory. More than 100 units were sold during its production run.
A CDC 6600 is currently on display at the Computer History Museum located in Mountain View, California. The sole operational CDC 6000 series system was restored by Living Computers: Museum + Labs, an institution that has since permanently closed.
History and impact
The origins of CDC’s product line trace back to designs developed at Engineering Research Associates (ERA), which were refined by Seymour Cray after he joined CDC. Following the experimental Little Character project in 1960, CDC introduced the CDC 1604, one of the earliest commercial computers utilizing transistors and among the fastest available at that time. While company leadership focused on creating a business-oriented lineup with improved character processing and record management capabilities, Cray envisioned a machine that would be fifty times faster than the 1604. He set an ambitious five-year objective to build "the largest computer in the world," equating size with computational speed.
Cray and his engineering team experimented with enhanced versions of the inexpensive transistors used in the 1604 but discovered that germanium transistors had inherent speed limitations. The resulting business-focused CDC 3000 series pushed these components to their maximum potential. Subsequently, Cray shifted attention to silicon-based transistors from Fairchild Semiconductor, which provided markedly better switching speeds.
As CDC grew, disagreements emerged between Cray and corporate management regarding project priorities. By 1962, as production neared for the CDC 3600, aligning with management’s goals, Cray threatened to depart unless granted full control over his work. CEO William Norris consented to establish an independent laboratory for Cray, who then relocated to Chippewa Falls, Wisconsin.
Although this relocation caused delays in developing new models, it allowed Cray’s team to advance rapidly without managerial constraints. Utilizing reliable new transistors, the CDC 6600 was developed under Cray’s leadership alongside system architect Jim Thornton. Between 1964 and 1969, over a hundred CDC 6600 units were sold, supporting nuclear weapons laboratories and academic institutions. Notably, a CDC 6600 disproved Euler's sum of powers conjecture through direct computational search.
Following this success, Cray immediately pursued a tenfold increase in performance with the development of the CDC 7600. Later models in the CDC Cyber series—specifically the 70 and 170 lines—retained much of the CDC 6600’s architecture and offered nearly complete backward compatibility.
The CDC 6600’s speed was triple that of IBM’s previous leader, the IBM 7030 Stretch, causing significant concern at IBM. Then-CEO Thomas Watson Jr. expressed regret over losing technological leadership despite IBM’s substantial resources, remarking on CDC’s small development team of only thirty-four engineers. Cray famously responded: "It seems like Mr. Watson has answered his own question."
Description
During the 1950s and 1960s, most computers relied on a single central processing unit (CPU) to control all system operations. Programs typically involved loading data into memory, performing computations, and then writing results back, necessitating complex CPUs capable of handling every instruction. This complexity increased the physical size of CPUs and caused signalling delays, which constrained performance by limiting the maximum cycle speed.
Cray adopted an alternative strategy. At that time, CPUs generally operated at slower speeds than the main memory they accessed; for instance, a processor might require 15 cycles to multiply two numbers, while memory access took only one or two cycles. Consequently, main memory remained idle for significant intervals—a situation the CDC 6600 capitalized on.
The CDC 6600 featured a streamlined central processor (CP) designed specifically for rapid arithmetic and logical tasks by reducing wiring length and minimizing signalling delays. This approach resulted in its distinctive cross-shaped chassis with CPU circuit boards positioned centrally, yielding a much smaller CPU footprint. Paired with faster silicon transistors, the CPU achieved a clock speed of 10 MHz (100 ns cycle time), roughly ten times faster than its rivals. Additionally, it executed instructions more efficiently; for example, multiplication was completed in just ten cycles.
Supporting this CPU were ten 12-bit 4 KiB peripheral processors (PPs), each connected to a shared set of 12 input/output (I/O) channels. The PPs handled I/O operations and managed data transfers into central memory for the CP. By accessing memory concurrently with CPU activity, they facilitated I/O processing without occupying central processing resources, thereby maximizing CPU efficiency.
The 6600's CP processed data in 60-bit words using a ones' complement integer format—a design choice preserved in subsequent CDC models through the late 1980s—making these systems among the last to utilize this representation outside certain digital signal processors.
CDC later introduced configurable options for CPs, PPs, and channels; for example, the CDC 6700 incorporated two central processors: a 6400 CP alongside a 6600 CP.
Unlike many contemporaries that featured elaborate front panel controls, the 6600 was equipped solely with a dead start panel. Its system console consisted of dual CRT displays managed by the operating system rather than direct hardware control.
The CDC 6600 contained approximately 400,000 transistors in total.
Peripheral processors
Instead of employing a complex instruction set within the CPU as was common at the time, the CDC 6600's processor executed a limited range of simple instructions. Cray delegated auxiliary functions such as memory management and input/output handling to dedicated peripheral processors (PPs), each running simpler instruction sets. This separation allowed the CPU to maintain a reduced instruction set—a pioneering example of what later became known as reduced instruction set computer (RISC) architecture.
This design permitted simultaneous operation of the CPU, PPs, and I/O processes, greatly boosting overall system performance without incurring high costs. The ten PPs were based on the straightforward 12-bit CDC 160-A architecture; although they ran at slower speeds than the CPU, they efficiently conducted data transfers in bursts to main memory through specialized hardware.
Physically, only one PP CPU existed; it multiplexed hardware resources among ten virtual PPs by employing a register barrel mechanism that cycled through each PP's state. Completing one full cycle across all PPs took 1000 nanoseconds (100 ns per PP), with instructions requiring anywhere from one to five or more cycles to finish.
Instruction Set Architecture of the Central Processor
The 6600 CPU embodied a Reduced Instruction Set Computing (RISC) philosophy, emphasizing straightforward instructions with clearly defined memory access patterns. This contrasted with other systems that implemented complex instructions combining multiple operations into single commands.
Instruction lengths were either 15 bits, divided into five 3-bit fields (f, m, i, j, k), or 30 bits, consisting of fields f, m, i, j plus an 18-bit K segment. The opcode was typically determined by the function (f) and modifier (m) fields. Most 15-bit instructions manipulated two registers and stored the outcome in a third register, whereas the majority of 30-bit instructions involved one register operand combined with a constant value.
The CP did not feature explicit load or store instructions; only jump and SAi instructions accessed memory directly. The SAi instruction transferred data between central memory and X registers (i=1–5 for reading into registers, i=6–7 for writing from registers). Consequently, performing an addition involving memory required two separate instructions. Although this design could theoretically increase instruction counts and reduce speed, the system’s parallel execution capabilities offset potential slowdowns. This architecture encouraged programmers to reduce memory interactions to optimize performance. The CDC 6600 CP supported three-address instructions, enabling specification of all operands within a single instruction.
Models
The CDC 6000 series included four principal models: the CDC 6400, CDC 6500, CDC 6600, and CDC 6700. The primary distinction among these was their CPUs—either the 6400 CPU or the 6600 CPU. The 6400 CPU utilized a single arithmetic unit without separate functional units, which meant instructions executed sequentially without overlap, accumulating their execution durations. In contrast, the 6600 CPU contained multiple functional units capable of concurrent operation, allowing overlapping instruction execution and thus accelerating processing speed. For instance, an addition instruction could commence immediately after starting a multiplication instruction, making total processing time equal to that of the longer-running instruction. The 6600 CPU also incorporated an instruction stack—a form of cache—to diminish idle periods caused by memory fetch delays. Both CPUs maintained instruction compatibility to ensure software portability across models while offering enhanced performance on the 6600 CPU. Model configurations included one 6400 CPU in the CDC 6400; two 6400 CPUs in the CDC 6500; one 6600 CPU in the CDC 6600; and a combination of one 6600 CPU plus one 6400 CPU in the CDC 6700.
Central Processor (CP)
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The CDC models—6400, 6500, and 6600—utilized a Central Processor and main memory organized around a word size of sixty bits. Within the CP resided eight general-purpose 60-bit operand registers labeled X0 through X7, eight 18-bit address registers named A0 to A7, and eight 18-bit increment registers designated B0 through B7. Notably, B0 was hardwired to zero by design hardware. Programmers commonly set B1 to one for ease of use.
Peripheral Processors handled all input/output tasks rather than the CP itself. Memory load and store operations were side effects triggered by modifying specific A registers: changing registers A1 through A5 caused data to be loaded from memory into corresponding X registers (X1–X5), while altering A6 or A7 resulted in storing data from X6 or X7 back to memory. Data movement was managed by a dedicated hardware unit called the "stunt box," which operated independently of instruction execution. This arrangement improved throughput despite typical memory access delays requiring eight cycles.
The CDC 6600’s Central Processor featured ten functional units capable of parallel operation—a groundbreaking superscalar architecture for its time. Unlike modern pipelined units where stages overlap, these units remained occupied throughout each instruction's entire execution period. Instructions could be issued every clock cycle (~100 nanoseconds), with decoding generally completing faster than execution itself. The functional units included:
- Two floating-point multipliers
- One floating-point divider
- One floating-point adder
- One long integer adder
- Two incrementer units responsible for memory load/store operations
- One shift unit
- One Boolean logic unit
- One branch unit
Floating-point computations were central to this design philosophy. Remarkably, the CDC 6600 executed full-precision floating-point multiplications in approximately the same duration as branch instructions. Examination of architectural documentation indicates that its Floating Point Unit incorporated a two-stage pipeline.
Fixed-point addition and subtraction employed ones' complement arithmetic within the Long Add Unit. Fixed-point multiplication was performed using the floating-point multiply unit by interpreting operands as single-precision floating-point numbers with zero exponent fields, producing a forty-eight-bit integer result. Integer division was implemented through macros that converted integers into floating-point format for processing.
An instruction cache known as the "stack," holding eight words of recently executed instructions, accelerated execution by reducing memory fetches during jumps within this cache. Unconditional jumps cleared this cache and were typically implemented as always-taken conditional jumps to optimize loop efficiency.
Operating on a four-phase clock running at roughly ten megahertz, this system achieved an approximate throughput of three million floating-point operations per second (MFLOPS). Later improvements in FORTRAN compilers enabled sustained performance near half a MFLOPS on practical application workloads.
Memory organization
User applications interact with a single contiguous segment of main memory, governed by the RA (Relative Address) and FL (Field Length) registers, which remain inaccessible to the user. When accessing address a, the processor verifies that a falls within the range 0 to FL-1; if valid, it references memory at RA + a. This base-bound relocation mechanism allows each program to perceive memory as a continuous block starting at zero, even though its physical location may vary. Attempts to access memory outside these bounds result in an interrupt and program termination, with the operating system potentially producing a core dump for troubleshooting. Unlike virtual memory, the entire addressable region must be contiguous within core memory and fit inside physical memory constraints.
Most CDC 6000 series models (except the initial seven) supported Extended Core Storage (ECS), a larger but slower core memory implemented with fewer wires per core element. ECS facilitated wide block transfers at speeds comparable to central memory and was directly accessible by the CPU for rapid operations. The operating system managed ECS using RA/FL registers similarly to regular core memory. ECS was utilized for large user data arrays, file caching, swapping activities, and communication between mainframes in multi-machine configurations.
Peripheral Processors (PPs)
To relieve the central CPU from system overhead, Cray incorporated ten Peripheral Processors (PPs), derived from the CDC 160-A design. These dedicated processors managed I/O operations and executed substantial parts of the operating system, thus freeing the Central Processor to focus on user-level programs. Only PPs had direct access to I/O channels; PP0 oversaw overall machine control including running the main CPU program, while other PPs handled specific I/O responsibilities—PP9 was assigned to the system console. The CPU placed OS requests into a designated memory location monitored by PP0, which could delegate tasks to other PPs and signal completion by clearing this location.
The exclusive control held by PP0 created a potential single point of failure; this vulnerability was resolved in the follow-up 7600 model where any PP could assume control dynamically, allowing reassignment as needed.
Each PP contained 4096 words of 12 bits each for local storage of I/O buffers and program code. The execution units were shared among all ten PPs through a "Barrel and slot" scheme, executing instructions in round-robin sequence. This approach reduced hardware costs and accommodated slower access times to central processor memory, which required multiple PP clock cycles before data could be retrieved again.
Central Processor access
In addition to their standard instruction set, peripheral processors (PPs) possess specific instructions for interacting with the central processor (CP):
CRD d– transfers a single 60-bit word from central memory at the address contained in the PP's A register into five consecutive PP words beginning at address d.CRM d,m– moves a block of words whose length is stored at location d into PP memory starting at address m.CWD d– collects five consecutive PP words from location d and writes them as one 60-bit word into central memory at the address held in register A.CWM d,m– copies a block starting at PP address m into central memory; the CP target address and block length are stored in register A and location d, respectively.RPN– copies the contents of the CP's program address register into the PP's A register.EXN("Exchange Jump") – triggers a CP task switch by sending an address from the A register; this interrupts the processor, loads registers from that address, and saves previous register contents there.
Wordlengths and Characters
The central processor (CP) operates with 60-bit words, while peripheral processors (PPs) utilize 12-bit words, which CDC referred to as "bytes." Characters are encoded in 6 bits, and CP instructions vary in length between 15 and 30 bits; the longer instructions incorporate a signed 18-bit address field. This architecture allows direct addressing of up to 128K words of main memory—equivalent to just under one megabyte by modern standards. Although subsequent CDC 6000-compatible models supported larger memory capacities, individual programs remained confined to the 128K word limit. Instruction alignment on word boundaries was required for jumps and subroutine returns, occasionally necessitating no-operation instructions; however, experienced programmers often replaced these with useful operations to enhance performance.
CDC employed a 6-bit character encoding system known as CDC display code, enabling storage of up to ten characters within each 60-bit word. The character set consisted of 64 symbols, including uppercase letters, digits, and punctuation marks adequate for FORTRAN programming and financial or scientific documentation. Two variants existed: one 64-character set that disregarded trailing colons, and a complementary 6/12 display code utilized in CDC Kronos and NOS (operating system) time-sharing environments to provide full ASCII compatibility while preserving backward compatibility.
Due to the absence of byte-addressable instructions, software had to explicitly pack and shift characters into word-sized units. The combination of large word widths and limited memory resources encouraged bit-level data packing. Processing entire words containing multiple characters was often more efficient than unpacking them individually; for instance, CDC’s COBOL compiler leveraged this approach for decimal field handling—a technique that has parallels in contemporary vector instruction sets such as AVX.
Physical Design
The hardware was housed in a cabinet shaped like a plus sign, with each arm’s outer section containing a pump and heat exchanger. Cooling was achieved through circulating Freon, which transferred heat to an external chilled water system. Each arm accommodated four chassis, approximately thick, hinged to open similarly to a book. The central "plus" area was densely packed with cables connecting chassis numbered from 1—which contained all ten PPUs, their memories, and twelve minimal I/O channels—to chassis number 16. Main memory modules were distributed among multiple chassis; systems equipped with only 64K words omitted one arm entirely.
Logic circuits were assembled into square modules measuring thick, featuring 30-pin connectors and six test points. These modules were sandwiched between aluminum cold plates, allowing for dense component packaging with excellent thermal conductivity but limited ease of repair, employing cordwood construction techniques.
Operating System and Programming
The operating system development for the 6600 encountered significant setbacks. Initially, it ran a straightforward batch job control system called COS (Chippewa Operating System), quickly adapted from the CDC 3000 series to facilitate testing. The intended operating system was SIPROS (Simultaneous Processing Operating System), developed by CDC’s System Sciences Division in Los Angeles; it promised advanced capabilities and was included in many customer contracts.
Delays in SIPROS development resulted in costly penalties and its eventual cancellation. Developers working on COS remained skeptical of SIPROS and continued improving COS independently.
This divergence led OS development down two paths: the officially endorsed evolution of COS at Sunnyvale produced SCOPE (Supervisory Control Of Program Execution). Various SCOPE versions introduced device support, permanent files, remote batch processing, and time-sharing functionalities but suffered from reliability problems. Concurrently, an unofficial iteration named MACE was developed at the Arden Hills facility by a single programmer during off-hours; it enhanced modularity and adapted to new storage hardware. Although never officially released, MACE became widely used among customers.
MACE later served as the foundation for Kronos, which added TELEX time-sharing and BATCHIO remote batch features while maintaining the COS/SCOPE file system with permanent files.
CDC sought to consolidate SCOPE and Kronos into NOS (Network Operating System), positioning it as the universal OS for all CDC machines. Despite this effort, many customers continued relying on SCOPE; consequently, CDC rebranded it as NOS/BE (Batch Environment) to project unified adoption. In practice, incorporating SCOPE features into Kronos proved simpler than integrating Kronos capabilities into SCOPE.
Additional internal OS utilities included SMM for hardware diagnostics, KALEIDOSCOPE for software smoke testing, and MALET (Maintenance Application Language for Equipment Testing), which field engineers used to stress test components utilizing error-marked media.
CDC reused the names SCOPE and COMPASS across both the CDC 6000 series (including the 6600) and the CDC 3000 series:
- COMPASS denoted assembly languages applicable to both families.
- SCOPE referred to implementations on both series.
CDC 7600
Originally designated as the CDC 6800, the CDC 7600 was planned to maintain full compatibility with the 6000-series systems. Nevertheless, the design team chose to emphasize enhanced performance rather than strict compatibility. As a result, the CPU maintained instruction-level compatibility with the 6400 and 6600 models—facilitating portability of high-level language source code—while its hardware architecture, particularly within the Peripheral Processor Units (PPUs), underwent substantial changes. This necessitated the development of a new operating system. This strategic shift enabled advancements beyond the 6000-series framework, including a decreased dependence on Peripheral Processors (PPs) for managing system control. In contrast to the 6600 CPU, the CDC 7600's processor incorporated a Central Exchange jump (XJ) instruction that could autonomously swap all register contents with core memory. This feature was subsequently backported to earlier machines in the 6000 series.
See also
Further reading
- Grishman, Ralph (1974). Assembly Language Programming for the Control Data 6000 Series and the Cyber 70 Series. New York, NY: Algorithmics Press.
- Control Data 6400/6500/6600 Computer Systems Reference Manual
- Thornton, J. (1963). Considerations in Computer Design – Leading up to the Control Data 6600
- Thornton, J. (1970). Design of a Computer—The Control Data 6600. Glenview, IL: Scott, Foresman and Co.
- (1990) Understanding Computers: Speed and Power, Time Life series
External links
- Interview with Neil R. Lincoln and 18 CDC engineers on computer architecture, Charles Babbage Institute, University of Minnesota.
- Parallel operation in the CDC 6600, James Thornton
- Presentation of the CDC 6600 and other Seymour Cray designs – by C. Gordon Bell of Microsoft Research
- Overview of CDC 6600's five-year reign as world's fastest computer at Computer History Museum