CVAX
| Industry | Computer hardware |
|---|---|
| Founded | November 8, 1957 |
| Products | CVAX microprocessor chipset, including CVAX 78034 CPU, CFPA floating-point co-processor, CVAX clock chip, CVAX System Support Chip (CSSC), CVAX Memory Controller (CMCTL), CVAX Q-Bus Interface Chip (CQBIC) |
| Website | www |
The CVAX refers to a microprocessor chipset created by Digital Equipment Corporation (DEC) that implements the VAX instruction set architecture (ISA). This chipset comprises the CVAX 78034 CPU, the CFPA floating-point co-processor, the CVAX clock chip, and several supporting components: the CVAX System Support Chip (CSSC), the CVAX Memory Controller (CMCTL), and the CVAX Q-Bus Interface Chip (CQBIC).
CVAX 78034
Known also as the MicroVAX 78034, the CVAX 78034 represents DEC's second-generation single-chip VAX microprocessor, launched in late 1987. It runs at 12.5 MHz (80 ns cycle) in high-performance models like the VAX 6000 Model 200, while operating at 11.11 MHz (90 ns cycle) in more cost-effective systems such as the MicroVAX 3500 and 3600.
This processor marked DEC’s initial use of on-chip caches for VAX CPUs, featuring a unified 1 KB instruction and data cache implemented with one-transistor DRAM, which significantly reduced cache size compared to standard SRAM approaches. Additionally, it was supported by an external cache of 64 KB.
The chip contains approximately 134,000 transistors on a die measuring 9.7 by 7.4 mm (totaling 71.78 mm2). It was manufactured using DEC’s CMOS-1 fabrication process, characterized by a 2.0 μm CMOS technology with two layers of aluminium interconnects. The processor is housed in an 84-pin ceramic package equipped with a heat sink, powered by a +5 V supply, and consumes up to 1.5 W.
Architecturally, the CPU is microprogrammed and partially pipelined, consisting of six principal units: the I-Box, E-Box, M-Box, bus interface unit (BIU), cache subsystem, and control store with its microsequencer. The I-Box is responsible for fetching and decoding VAX instructions via an Instruction decode ROM (IROM).
Within the E-Box reside a register file comprising thirty-one single-read/single-write registers and eight dual-read/single-write registers, a 32-bit program counter, a constant generator, a shifter, and a 32-bit arithmetic logic unit (ALU) capable of both arithmetic and logical operations. The ALU also includes a shifter dedicated to integer multiply and divide instructions.
The M-Box oversees memory management through a fully associative translation look-aside buffer (TLB) with 28 entries for virtual-to-physical address translation. It cooperates closely with the BIU, which manages access to the internal cache and interfaces with an external multiplexed 32-bit address/data bus.
The control store contains a ROM consisting of 1,600 words of 41 bits each, subdivided into fields that control various functional units as well as the microsequencer. Departing from the X-shaped cells used in its predecessor, the MicroVAX 78032, this model employs conventional H-shaped cells. The microsequencer generates microaddresses to orchestrate operations across all functional units.
CFPA
The CFPA (CVAX Floating Point Accelerator) serves as a floating-point coprocessor designed specifically for use with the CVAX 78034.
It incorporates roughly 65,000 transistors on a die sized at 7.3 by 9.1 mm (66.43 mm2), produced using DEC’s initial CMOS fabrication technology (CMOS-1), which features a 2.0 μm process with two aluminium interconnect layers. The CFPA is packaged within a 68-pin surface-mount chip carrier.
CVAX+
CVAX+ represents an optical shrink of the original CVAX chipset achieved through DEC’s second-generation CMOS process (CMOS-2), which uses a finer 1.5 μm technology with two wiring layers. The design team focused on reducing the size of the CVAX 78034 CPU, CFPA floating-point accelerator, and CMCTL memory controller chips while leaving other components unchanged. The downsized version of the 78034 was designated CVAX-60, with its tape-out completed in August 1987 ahead of mass production for the original chip; shortly after, in November 1987, the CFPA-60 was released. Operating at an increased clock speed of 16.67 MHz, CVAX+ maintained comparable power consumption levels.
Launched toward the end of 1988, CVAX+ served to enhance entry-level CVAX systems and functioned as an interim solution for upgrading VAX 6000 models during delays encountered in Rigel processor manufacturing.
SOC
SOC combined the CVAX 78034, CFPA, clock generator, and an 8 KB secondary cache within a single chip. Released in 1990 and running at 25 or 28.5 MHz, it was designed for entry-level servers, workstations, VXT-2000 X terminals, as well as embedded uses in DEC's advanced printers and terminals. Manufactured using DEC's third-generation CMOS technology (CMOS-3), it utilized a 1.0 μm fabrication process featuring three metal layers.