VAX 6000
| Industry | Computer hardware |
|---|---|
| Founded | 1957 |
| Headquarters | Maynard , United States |
| Products | VAX 6000 series minicomputers |
The VAX 6000 series, now discontinued, comprised a range of minicomputers developed by Digital Equipment Corporation (DEC) utilizing processors based on the VAX instruction set architecture (ISA). Originally intended to serve as a mid-tier option alongside the VAX 8000, the VAX 6000 Model 400 series ultimately superseded the VAX 8000 by delivering somewhat enhanced performance at approximately half the expense. This system supports Digital’s VMS and ULTRIX operating systems.
Cabinet
The cabinet of the VAX 6000 houses three upper card cages: on the right side, a 14-slot XMI cage accommodates CPU and memory modules, while the left side contains optional VAXBI Bus components. Two platform variants were produced—XMI-1 and XMI-2—differentiated by their VAXBI bus arrangements. The XMI-1 platform necessitated a DWMBA adapter along with two separate 6-slot VAXBI channels, whereas the XMI-2 provided an optional single 12-slot VAXBI channel. Both configurations utilized two 6-slot VAXBI card cages.
Beneath these card cages, the majority of the cabinet’s interior volume was dedicated to cooling mechanisms. The base section could be equipped with an optional battery backup unit as well as two RA90 or RA92 hard disk drives. This battery backup system supplied power for one second during outages, enabling cache and memory contents to be retained for up to ten minutes afterward.
The cabinet’s dimensions measured high, wide, and deep, with a total weight of .
VAX 6000 Model 2x0
- Previously known as the VAX 62x0
- Code name: "Calypso"
- Released on 19 April 1988
- Equipped with one to four 12.5 MHz (80 ns cycle) CVAX chip sets, each including 256 KB of external secondary cache composed of 160 ns SRAM
- The digit "x" indicates the number of chip sets installed
- Supported up to 256 MB ECC memory
VAX 6000 Model 3x0
- Formerly called the VAX 63x0
- Code name: "Hyperion"
- Released on 24 January 1989
- Configured with one to six KA62B CPU modules, each containing a 16.67 MHz (60 ns cycle) CVAX+ chip set and a 256 KB external secondary cache operating at 8.33 MHz (120 ns)
- The value of "x" corresponds to the number of CPU modules
- Maximum memory capacity of 256 MB ECC
VAX 6333
The VAX 6333 represented a preassembled VAXcluster consisting of three VAX 6330 (Model 330) systems. Sold together with the SA650 Storage Array, it carried a price tag of US$2.8 million.
VAX 6000 Model 4x0
Released on 11 July 1989 under the code name "Calypso/XRP", the Model 4x0 featured the KA64A CPU module which could be configured with between one and six processors. This module incorporated a Rigel chipset running at 35.71 MHz (28 ns cycle) and included an external 128 KB B-cache (L2 cache). The direct-mapped B-cache used a line size of 64 bytes and was constructed from twenty-four units of 64 KB SRAM with a speed of 15 ns. Additionally, the module integrated the REXMI chipset that connected the Rigel DAL bus to the XCI ASIC, then routed through the XCA controller/address chip and two XCP data path chips, all manufactured using Digital's CMOS-2 technology. Memory support reached up to 256 MB ECC.
VAX 6000 Model 5x0
- Code-named "Calypso/XMP"
- Introduced on 25 October 1990
- Configurable from one to six KA65A CPU modules, each powered by a Mariah chipset running at 62.5 MHz (16 ns cycle) with a 512 KB external secondary cache
- Supported maximum memory capacity of up to 512 MB ECC
VAX 6000 Model 6x0
Known by the codename "Neptune" and launched on 30 November 1991, the Model 600 incorporated the KA66A CPU module, which housed an 83.33 MHz (12 ns cycle) NVAX microprocessor paired with a 2 MB external B-cache (L2 cache). The system architecture allowed for one to six CPU modules, with the NVAX processor interfacing through the NDAL bus to the NEXMI ASIC. This ASIC converted NDAL signals into XMI2 bus commands and controlled peripheral devices via ROMBUS. The NEXMI ASIC was a semi-custom CMOS-3 chip containing approximately 250,000 transistors, packaged in a specialized ceramic pin grid array. Memory capacity was expandable up to 1 GB.