DEC 3000 AXP
| Company type | Product line |
|---|---|
| Industry | Computer workstations and servers |
| Predecessor | DECstation |
| Founded | 1992 |
| Defunct | 1995 |
| Successor | AlphaStation, AlphaServer |
| Owner | Digital Equipment Corporation |
DEC 3000 AXP refers to a lineup of computer workstations and server systems manufactured by Digital Equipment Corporation between 1992 and approximately 1995. These machines were among the earliest to utilize the 64-bit Alpha AXP architecture. Supported operating environments included DEC OSF/1 AXP (which was later rebranded as Digital UNIX) and OpenVMS AXP (subsequently known as OpenVMS).
Every model in this series incorporated either the DECchip 21064 (EV4) or the DECchip 21064A (EV45) processors. They also integrated design elements from previous MIPS architecture-based DECstation platforms, such as the TURBOchannel bus and the associated I/O framework.
By late 1994, the DEC 3000 AXP line was succeeded by the AlphaStation series for workstations and the AlphaServer family for server applications.
Models
This product range consisted of three distinct model groups, internally referred to by Digital as "the seabirds," with codenames Pelican, Sandpiper, and Flamingo.
| Model | Codename | CPU | CPU MHz | B-cache (L2) | Chassis | Introduced | Withdrawn |
|---|---|---|---|---|---|---|---|
| Model 300 | Pelican | EV4 | 150 | 256 KB | Desktop | 1993-04-20 | ? |
| Model 300L | Pelican | EV4 | 100 | 256 KB | Desktop | 1993-04-20 | 1994-03-25 |
| Model 300X | Pelican+ | EV4 | 175 | 256 KB | Desktop | 1994-02-08 | 1995-10-02 |
| Model 300LX | Pelican+ | EV4 | 125 | 256 KB | Desktop | 1994-02-08 | 1995-06-23 |
| Model 400 | Sandpiper | EV4 | 133 | 512 KB | Desktop | 1992-11 | ? |
| Model 500 | Flamingo | EV4 | 150 | 512 KB | Pedestal | 1992-11 | ? |
| Model 500X | Hot Pink | EV4 | 200 | 512 KB | Pedestal | 1993-04-20 | ? |
| Model 600 | Sandpiper+ | EV4 | 175 | 2 MB | Desktop | 1993-10-13 | 1995-10-02 |
| Model 700 | Sandpiper45 | EV45 | 225 | 2 MB | Desktop | 1994-07-21 | 1995-10-02 |
| Model 800 | Flamingo II | EV4 | 200 | 2 MB | Pedestal | 1993-10-13 | 1994-02-12 |
Note: Server variants of Models 400, 500, 600, 700, 800, and 900 carried an "S" suffix.
Description
In systems based on Flamingo and Sandpiper designs, the logic components are divided into two separate modules: a larger CPU module and an I/O module, which are linked through a connector with 210 pins. Conversely, Pelican systems feature a CPU daughterboard that plugs into a system module containing both the processor and the B-cache (L2 cache).
The core of Flamingo and Sandpiper architectures is a crossbar switch realized through an ADDR ASIC, four SLICE data slice ASICs, and a TURBOchannel (TC) ASIC. This setup enables connections between buses of varying widths to facilitate subsystem data transfers. Control functions—including cache management, memory operations, and TURBOchannel control—are entirely implemented with PAL devices. In contrast, Pelican models employ a more conventional workstation design that utilizes buses and buffers similar to those found in later versions of DECstation Personal workstations.
Memory
Both Sandpiper and Flamingo platforms utilize proprietary Fast Page Mode SIMM modules with a unique configuration: they are built on a 100-pin form factor supporting a total of 40 bits (32 bits for data plus an additional eight bits for ECC). These SIMMs come in capacities ranging from 2 MB up to 32 MB. Memory is organized in eight-way interleaving to achieve a wide memory bus of 256 bits. The Sandpiper supports up to half a gigabyte of RAM by employing two banks of eight SIMMs each; Flamingo doubles this capacity by incorporating four such banks for a maximum of one gigabyte. The Pelican line targets more cost-sensitive users by using standard eight-slot banks of conventional 72-pin Fast Page Mode SIMMs. These modules provide longword parity protection instead of ECC and range from sizes of eight MB to thirty-two MB per SIMM. Memory in Pelican systems is two-way interleaved, delivering a total bus width of sixty-four bits and supporting up to two hundred fifty-six MB of RAM overall.
Expansion slots
The DEC 3000 AXP lineup utilizes a 32-bit TURBOchannel bus operating at frequencies ranging from 12.5 MHz in the 300 series to 25 MHz in models 500 through 900. An ASIC bridges the TURBOchannel with the SLICE data path ASICs. The quantity of expansion slots varies by model: most 300 series units include two slots (with the exception of the 300L, which has none), models 400, 600, and 700 come with three slots; the 500X offers five slots; and models 500, 800, and 900 provide six expansion slots.
Graphics
Integrated CXTurbo graphics are standard on the system module for the 300 series as well as models 500, 500S, and 500X—essentially functioning as an onboard HX TURBOchannel option card. This setup contains an SFB ASIC, a Brooktree Bt459 RAMDAC, and 2 MB of VRAM. Additionally, the Model 500 variants include a 256 KB flash ROM that stores part of the firmware. Display resolutions can reach up to 1280 × 1024 pixels with refresh rates varying between 66 Hz and 72 Hz depending on the specific model.
Because of architectural parallels with the DECstation family, graphics options designed for DECstation TURBOchannel systems—including framebuffers and accelerated 2D/3D graphics—are fully compatible with DEC 3000 AXP machines. Users can install up to three identical framebuffers to enable multi-monitor configurations.
Subsequent graphics solutions were created solely for the DEC 3000 AXP series, such as Digital’s ZLX-E1/E2/E3, ZLX-L1/L2, ZLX-M1/M2 PixelVision-based accelerated graphics line, and Kubota’s premium Denali subsystem. The Denali is an external chassis housing as many as six geometry engines alongside multiple memory modules, delivering sophisticated real-time 3D rendering capabilities like interactive volume visualization via its TURBOchannel interface.
I/O subsystem
The DEC 3000 AXP’s input/output subsystem includes support for Ethernet, ISDN, audio input/output, four serial communication lines, and a real-time clock. This subsystem connects to the TURBOchannel through the IOCTL ASIC, which controls two separate 8-bit buses named IOBUS HI and IOBUS LO; these can be combined into a single 16-bit bus to increase data throughput. Ethernet functionality is provided by an AMD Am7990 LANCE controller paired with an Am7992 SIA supporting either 10BASE-T or AUI connections, along with an ESAR chip that stores the MAC address. Notably, the Am7990 interfaces with IOCTL via a unique 16-bit connection. ISDN services and telephone-grade audio are managed by an AMD Am79C30A DSC chip. Four serial ports are available through two Zilog Z85C30 SCC dual UART devices, while timekeeping is maintained by a Dallas Semiconductor DS1287A real-time clock.
SCSI interface
The connection between SCSI controllers and the TURBOchannel bus in the DEC 3000 AXP is facilitated by a TCDS (TURBOchannel Dual SCSI) ASIC. Early units in the 300 series featured a single NCR 53C94 controller; models 400 and 500 incorporated two controllers, each offering one or two single-ended SCSI buses running at 5 MB/s with an 8-bit width. Higher-end versions such as models 600, 700, 800, and 900 are equipped with two NCR 53CF94-2 controllers that provide faster single-ended SCSI buses operating at speeds up to 10 MB/s on an 8-bit data path.