DECstation
| Company type | Product line |
|---|---|
| Industry | Computer hardware |
| Predecessor | PDP-8 based word processing device (VT78) |
| Founded | 1978 |
| Headquarters | Palo Alto , United States |
Key people | James Billmaier, Mario Pagliaro, Armando Stettner, Joseph DiNucci |
| Products | MIPS-based computer workstations, word processing units |
| Parent | Digital Equipment Corporation (DEC) |
The DECstation name was used by DEC for three separate computer product lines. The first appeared in 1978 as a word processing device, while two additional series launched in 1989. These later versions comprised MIPS architecture-based computer workstations that operated on DEC’s own UNIX variant, ULTRIX, and early versions of OSF/1, along with a collection of PC compatible machines.
DECstation 78
The original DECstation series featured word processing units built around the PDP-8 processor, integrated within a VT52 terminal, commonly referred to as the VT78.
History
The second generation of DECstations debuted with the DECstation 3100, introduced on January 11, 1989, marking DEC's entry into the commercial RISC workstation market.
During the late 1980s, UNIX vendors utilizing RISC architectures, such as Sun Microsystems, began attracting users away from DEC’s traditional CISC-based VAX systems by offering roughly double the price-to-performance ratio. The DECstation 3100 originated from several internal initiatives aimed at competing effectively in this emerging sector.
Developed within DEC’s Palo Alto Hamilton Avenue skunkworks group (known as the PMAX project), this line sought to deliver competitive performance and cost efficiency comparable to Sun and other RISC UNIX workstations. Under the leadership of James Billmaier, Mario Pagliaro, Armando Stettner, and Joseph DiNucci, the team opted for the third-party MIPS architecture, rather than DEC’s own CISC VAX or the then-under-development DEC PRISM architectures.
After considering alternatives like the Intel i860 and Motorola 88000, MIPS was chosen due to its support for both big- and little-endian modes; ultimately, little-endian was selected to maintain compatibility with VAX and Intel platforms. Unlike VAX or later DEC Alpha processors, DECstations were designed specifically to run UNIX (ULTRIX), so MIPS incompatibility with VAX and OpenVMS was not problematic.
In 1989 alone, DEC sold over $1 billion worth of DECstations. The 3100 model led in price/performance with a suggested retail price of , translating to approximately $850 per million instructions per second—about 40% less expensive than equivalent Sun workstations. Despite initial reservations about relying on an architecture not owned by DEC, the company eventually transitioned away from MIPS-based DECstations in favor of its proprietary Alpha processors derived from PRISM technology.
Early Alpha models (such as the DEC 3000 AXP series) shared several features with MIPS-based DECstations, including use of the TURBOchannel expansion bus and compatible peripherals; these Alpha systems were marketed alongside the phasing-out DECstation line.
Plans for ECL-based DECstations powered by R6000 processors were abandoned in August 1990 after supplier Bipolar Integrated Technology failed to meet production goals; yield problems were exacerbated by DEC’s insistence on continued little-endian operation.
MIPS-based DECstations played a significant role as early development platforms for the Mach kernel microkernel and initial work on Windows NT. Later on, open-source operating systems such as NetBSD and Linux/MIPS helped extend their usability with modern OS support.
DEC initially intended to adopt OSF/1 as its primary UNIX operating system starting March 1992 but soon reverted focus back to ULTRIX on MIPS platforms while promoting OSF/1 for upcoming Alpha hardware. Models including the DECstation 2100, 3100 series, and 5000/120–200 were planned to run OSF/1 alongside select DECsystem machines.
Customer concerns over ambiguous OSF/1 support and ULTRIX’s future prompted revised commitments guaranteeing a production-quality OSF/1 release for all UNIX workstations in 1993, including those based on MIPS. However, internal corporate conflicts led to strategic uncertainty and delayed execution.
By late 1992, OSF/1’s deployment on MIPS hardware became doubtful due to budget constraints despite marketing arguments that sales losses would outweigh development expenses. Subsequent announcements confirmed cancellation of OSF/1 for DECstations and cast doubt on hardware upgrades beyond R4400-based models. Although an OSF/1 port was completed, it never reached commercial release. This situation eroded customer trust in both the DECstation line and ULTRIX, raising broader questions about DEC’s UNIX strategy.
Although introduced before embracing an Advanced Computing Environment (ACE) strategy, DEC suggested possible migration routes from ULTRIX to OSF/1 through SCO Open Desktop on MIPS platforms. Microsoft even demonstrated Windows NT running on Personal DECstations. During Alpha development, plans included binary compatibility with VAX and MIPS through the mx binary translator to enable running ULTRIX MIPS applications on Alpha-based OSF/1 systems.
The GXemul project provides emulation support for multiple DECstation models.
Models
Following the initial MIPS-based DECstation 3100, Digital introduced a more affordable variant known as the 2100. At its debut, the DECstation 3100 was promoted as the fastest UNIX workstation available worldwide, delivering performance approximately three times greater than the contemporary VAXstation 3100. Variants designed for server use, which omitted framebuffers or graphics accelerators and utilized either Turbochannel or Q-bus architectures, were labeled under the "DECsystem" brand. These should not be mistaken for the PDP-10 systems sharing the same designation.
Initial DECstation models were characterized by high integration but limited expandability, lacking any expansion buses. This limitation was overcome with the introduction of the DECstation 5000 series, which incorporated the TURBOchannel Interconnect and provided compatibility with ARC standards. The last iterations of DECstation systems featured increased integration through custom ASIC designs. Starting with the DECstation 5000 Model 240, discrete components were replaced by LSI ASICs, culminating in the Model 260 that employed a single VLSI ASIC to manage most control logic.
Suffixes attached to DECstation 5000 model numbers typically denoted their specific graphics capabilities.
DECstation 3100 and DECstation 2100
| Model and Codename | Processor | Clock Speed | Release Date | Discontinued |
|---|---|---|---|---|
| 3100 "PMAX" | R2000 with R2010 FPU and R2020 buffers | 16.67 MHz (60 ns) | 11 January 1989 | ? |
| 2100 "PMIN" | R2000 with R2010 FPU and R2020 buffers | 12.50 MHz (80 ns) | 11 July 1989 | ? |
Processor
Both the DECstation 3100 and 2100 are equipped with an R2000 CPU complemented by an R2010 floating-point coprocessor and four R2020 write buffers. The R2000 incorporates a 64 KB direct-mapped instruction cache alongside a 64 KB write-through data cache featuring a four-byte line size. The quartet of R2020 buffers functions as a four-stage write buffer, enhancing efficiency by permitting non-blocking writes to the data cache.
Configured for little-endian operation, these machines maintained compatibility with both the VAX architecture and Intel-based personal computers, facilitating broader interoperability across platforms.
Memory
The memory architecture of the DECstation 3100 and 2100 consists of system memory built from DRAM and framebuffers utilizing VRAM technology. System memory capacity ranges between 4 MB and 24 MB, arranged over six physical banks populated through twelve SIMM slots accommodating 2 MB SIMMs installed in pairs (increments of 4 MB). Memory is safeguarded by byte-level parity protection. Monochrome framebuffers employ a 256 KB VFB01 SIMM module, whereas color framebuffers use a larger 1 MB VFB02 SIMM; absence of these modules renders framebuffer functionality inoperative. SIMM slots are rated for up to twenty-five removal and insertion cycles, though five cycles are recommended for reliability.
Graphics
Graphical output is handled via two framebuffer options: a monochrome module providing a single-bit color depth at a resolution of 1024 × 864 pixels, and a color module offering eight-bit color at identical resolution. Both framebuffer types utilize the Brooktree Bt478 RAMDAC featuring three separate 256-entry, eight-bit color lookup tables. The hardware cursor is generated by the DC503 PCC chip, supporting a cursor size of 16 × 16 pixels with two-bit color depth. The color framebuffer additionally includes an eight-bit write mask ("planemask") enabling selective pixel updates. Although framebuffer memory is physically arranged as a 1024 × 1024 pixel array, only the uppermost 864 scan lines are actively displayed; unused portions can serve as storage for graphical elements such as fonts but do not confer any performance benefits compared to main memory usage. Framebuffer memory lacks parity error protection. Video output is provided through a DB15 male connector compatible with RS343A/RS170 signal standards.
Ethernet and SCSI
The onboard 10 Mbit/s Ethernet functionality is managed by an AMD 7990 LANCE controller paired with an AMD 7992 SIA interface, utilizing a BNC ThinWire connector. Network efficiency is improved by a 64 KB SRAM buffer. The MAC address is stored in a detachable Ethernet Station Address ROM (ESAR).
For SCSI connectivity, the interface supports single-ended transfers at 5 MB/s through a DC7061 SII gate array, supplemented by a 128 KB buffer to enhance data flow. This interface links to internal 3.5" drive bays as well as an external HONDA68 port designed for additional drive expansion units.
Other
The system includes four asynchronous serial communication lines managed by a DC7085 gate array; however, only the third line provides modem control signals. Available connectors consist of a 4-pin MMJ for the keyboard, a 7-pin DIN for the mouse, and two 6-pin MMJ ports designated for printer and modem connections. The real-time clock is powered by a Motorola MC146818 chip, which also offers 50 bytes of RAM allocated for console configuration data. Bootstrap and diagnostic software reside in two 128 KB ROMs housed in DIP sockets, totaling 256 KB of ROM memory.
Enclosure
Both the DECstation 3100 and 2100 models utilize the same chassis as the VAXstation 3100, sharing an identical system module. The enclosure accommodates two 3.5-inch drives mounted on trays positioned above the system module. Located on the left side, the system module shares space with the power supply unit, which occupies approximately one-quarter of the enclosure's interior.
Personal DECstation 5000 Series
Known by the codename "MAXine," the Personal DECstation 5000 Series represents entry-level workstations encased in a low-profile desktop design. The power supply is situated on the left side, while the front panel offers mounting options for either two fixed drives or one fixed drive alongside a diskette drive. System logic is divided across two printed circuit boards: a base system module containing most of the logic circuitry and a CPU module housing the processor.
Initial pricing started at $3,995 for a diskless 5000/20 model equipped with 8 MB of RAM and a 17-inch greyscale monitor.
| Model | Processor | MHz | Introduced | Discontinued |
|---|---|---|---|---|
| Model 20 | R3000A with R3010 chipset | 20 | 28 January 1994 | |
| Model 25 | R3000A with R3010 chipset | 25 | 28 January 1994 | |
| Model 33 | R3000A with R3010 chipset | 33 | 22 June 1992 | 28 January 1994 |
| Model 50 | R4000 | 50 | June 1993 | 28 January 1994 |
CPU module
There are three distinct CPU module variants, each containing the CPU subsystem. The initial version features an R3000A CPU running at either 20, 25, or 33 MHz paired with an R3010 floating-point unit. It incorporates separate direct-mapped caches for instructions and data—64 KB each—with cache lines sized at four bytes; notably, the data cache operates in write-through mode. All components function synchronously at the R3000A's clock frequency.
A CPUCTL ASIC serves as an interface and buffer between this faster CPU module and the slower system module clocked at 12.5 MHz. This ASIC also facilitates a TURBOchannel bus operating at 12.5 MHz to connect system components.
The second CPU module iteration modifies the first by utilizing plastic packaging for the R3000A and R3010 chips at speeds of either 20 or 25 MHz instead of ceramic packaging. The third version advances to an R4000 microprocessor featuring internal caches along with an additional secondary cache of one megabyte.
Memory
The system comes equipped with 8 MB of built-in memory and provides four SIMM slots for expansion, allowing a maximum capacity of 40 MB. These slots require SIMMs to be installed in pairs of either 2 MB or 8 MB modules, all matched in size. Memory access is handled by a Memory Control ASIC, which communicates with the CPU via the TURBOchannel bus on a 40-bit memory interface composed of 32 data bits and 4 parity bits.
Expansion
Expansion capabilities include two TURBOchannel slots, each capable of addressing up to 64 MB of physical memory space.
Graphics
The Personal DECstation features an 8-bit color frame buffer supporting a resolution of 1024 × 768 pixels at a 72 Hz refresh rate. Its video memory consists of 1 MB VRAM arranged as 262,144 units of 32-bit words, with each word representing four 8-bit pixels. Color output is managed by an INMOS IMS G332 RAMDAC equipped with a 256-entry, 24-bit color lookup table, enabling selection from a palette exceeding sixteen million colors. This frame buffer operates as an integral part of the system's memory architecture.
I/O subsystem
The input/output subsystem includes an 8-bit single-ended SCSI interface, a 10 Mbit/s Ethernet connection, serial communication ports, Serial Desktop Bus support, and analog audio functionality. The SCSI controller is an NCR 53C94 Advanced SCSI Controller; Ethernet connectivity is provided by an AMD Am7990 LANCE chip paired with an Am7992 SIA for AUI interface compatibility. Serial communication is facilitated through a Zilog Z85C30 SCC supporting baud rates from 50 to 19,200 with full modem control capabilities. Analog audio and ISDN functions are delivered via the AMD 79C30A DSC. All these components interface through the IOCTL ASIC, which links two separate 8-bit or one combined 16-bit I/O bus to the TURBOchannel interconnect.
DECstation 5000 Model 100 Series
| Model | Processor | Clock Speed (MHz) | Launch Date | End of Production |
|---|---|---|---|---|
| Model 120 | R3000A with R3010 chipset | 20 | ? | ? |
| Model 125 | R3000A with R3010 chipset | 25 | ? | ? |
| Model 133 | R3000A with R3010 chipset | 33 | ? | ? |
| Model 150 | R4000 | 100 | ? | ? |
Known internally as "3MIN," the DECstation 5000 Model 100 Series represents mid-tier workstations. Initial models utilize a R3000A CPU paired with a separate R3010 floating-point unit mounted on a daughter card. The Model 150 advances to a single R4000 processor that integrates the FPU on-chip. Models 120 and 125 feature distinct instruction and data caches of 64 KB each, whereas the Model 133 upgrades to a larger instruction cache of 128 KB.
Memory options span from 16 MB to a maximum of 128 MB through sixteen SIMM slots that accept either all-2 MB or all-8 MB modules; mixing sizes is not supported. The availability of compatible 2 MB SIMMs allows for economical upgrades from older DECstation models.
This series provides three TURBOchannel expansion slots and introduces the I/O Controller ASIC (IOCTL ASIC), which connects dual 8-bit I/O buses to the TURBOchannel running at 12.5 MHz.
DECstation 5000 Model 200 Series
Targeted at high-performance workstation users, the DECstation Model 200 Series also includes server variants—DECsystem Models 200, 240, and 260—that consist solely of CPU modules, system boards, and power supplies without internal disk drives. Storage needs are met externally via SCSI-connected drive arrays or network-attached file servers.
| Model and Codename | Processor | Clock Speed (MHz) | Release Date | Discontinued |
|---|---|---|---|---|
| Model 200 "3MAX" | R3000, R3010 chipset | 25 | 3 April 1990 | ? |
| Model 240 "3MAX+" | R3400 | 40 | December 1991 | No earlier than September 1994 |
| Model 260 "3MAX+" | R4400 | 60 | June 1993 | ? |
CPU subsystem
Each unit within the Model 200 Series incorporated a unique CPU subsystem. For instance, the Model 200’s CPU subsystem, located on the KN02 system module, consists of a chipset featuring the R3000 processor, R3010 floating-point unit, and R3220 MB (a six-stage write/memory buffer), along with external 64 KB instruction and data caches. The Model 240 employs a CPU daughter card containing a single 40 MHz R3400, which integrates the R3000A CPU and R3010 FPU. This is connected via a 40 MHz bus to 64 KB instruction and data caches and serves as the datapath to the MB ASIC. Meanwhile, the Model 260’s CPU module includes a 120 MHz (60 MHz external clock) R4000 processor with internal caches and an external secondary cache. Notably, this model houses the boot ROM firmware on the CPU module itself due to the specific requirements of the R4000.
The variations in CPU subsystems affected how DECstation upgrades were designed. Although "snap-in" R4000 upgrades were announced in 1992 for all existing DECstations, upgrading a Model 200 necessitated replacing the entire motherboard.
Memory subsystem
The Model 200 Series supports memory expansion through 15 SIMM slots on its system module, accommodating from 8 to 480 MB of RAM using proprietary 128-pin SIMMs available in either 8 MB or 32 MB sizes. All SIMMs installed must be uniform in capacity, enabling configurations ranging from 8 to 120 MB when using 8 MB modules or from 32 to 480 MB with 32 MB modules. Memory operates at a frequency of 25 MHz with a 32-bit data width matching the R3000’s word size and incorporates ECC error correction with seven check bits per 32-bit word.
Memory access is arranged in a two-way interleaved fashion using low-order address bits, effectively doubling throughput up to a peak of 100 MB/s. Additionally, an optional battery-backed 1 MB NVRAM disk cache can be installed in slot 14 to improve performance when supported by software.
Whereas the Model 200 relies on discrete components for memory control logic, the Model 240 replaces these with three ASICs: the MB ASIC interfaces between the CPU running at 40 MHz and system components at 25 MHz; the MT ASIC manages memory control functions such as refresh cycles, DMA operations, transactions, and ECC handling; and the MS ASIC routes control signals while generating the system clock. This ASIC integration reduces component complexity and optimizes memory management.
Expansion
Expansion capabilities in the Model 200 Series are provided via TURBOchannel Interconnect technology, with all models equipped with three TURBOchannel slots for options. The Model 200 allocates 4 MB of physical address space per TURBOchannel option slot, whereas both the Model 240 and Model 260 extend this to 8 MB per slot. TURBOchannel operates at a frequency of 25 MHz on the Model 240 and Model 260 systems, with control implemented by the MT ASIC.
I/O subsystem
The I/O architecture differs notably between the Model 200 and its successors, Models 240 and 260. In the Model 200, Ethernet and SCSI functionality are provided by two integrated TURBOchannel option modules: PMAD-AA for Ethernet connectivity and PMAZ-AA for SCSI support. The PMAD-AA module utilizes an AMD 7990 LANCE controller for managing 10BASE-T Ethernet connections through an AMD 7992 Serial Interface Adapter (SIA) and a BNC ThinWire connector. SCSI operations run over an NCR 53C94 ASC managing an 8-bit single-ended bus. Both modules include dedicated 128 KB SRAM buffers to boost performance. Four serial ports handle keyboard, mouse, communications port, and printer connections via two DC7085 UARTs. A Dallas Semiconductor DS1287 real-time clock with integrated NVRAM (50 bytes) and a system boot-strap plus diagnostic ROM of 256 KB complete this configuration.
Conversely, Models 240 and 260 employ an I/O Controller ASIC that bridges TURBOchannel to two I/O buses connecting devices such as dual Zilog Z85C30 SCCs, NCR 53C94 ASC for SCSI, AMD 7990 LANCE for Ethernet, Dallas DS1287 RTC, and system ROM. This ASIC was initially introduced in the earlier Model 100 series but operates at twice its original clock speed—25 MHz—in these later models. The I/O design developed here was subsequently adapted for use in the DEC 3000 AXP systems.
Graphics
DECstation computers equipped with TURBOchannel slots accommodated TURBOchannel-compatible framebuffers as well as both two-dimensional and three-dimensional graphics accelerators.
Framebuffers
- CX "Color Frame-Buffer Graphics Module", model PMAG-BA: delivers 8-bit color support at a resolution of 1024 × 864.
- HX "Smart Frame-Buffer Graphics Module", models PMAGB-BA/BC/BE: features a framebuffer incorporating a proprietary ASIC that provides limited yet rapid 2D acceleration.
- MX "Monochrome Frame-Buffer Graphics Module", model PMAG-AA: offers 1-bit color at 1280 × 1024 resolution with a refresh rate of 72 Hz.
- TX "True Color Frame-Buffer Graphics Module", models PMAG-JA and PMAGB-JA: both modules support 24-bit color at 1280 × 1024; the PMAG-JA operates at 66 Hz, while the PMAGB-JA runs at 72 Hz.
2D graphics accelerators
- PX "2D Graphics Accelerator": Utilizing the PixelStamp design but lacking the geometry engine, this accelerator was dedicated solely to enhancing 2D graphics performance. It was eventually replaced by the HX module in most scenarios.
3D graphics accelerators
Available options comprised:
- PXG ("Lo" or "Mid 3D Graphics Accelerator," dependent on configuration)
- PXG+ ("Lo Plus" or "Mid Plus 3D Graphics Accelerator")
- PXG Turbo ("Hi 3D Graphics Accelerator")
- PXG Turbo+ ("Hi Plus 3D Graphics Accelerator")
Every PXG model supported either 8-bit or 24-bit color at a resolution of 1280 × 1024, with refresh rates of either 66 or 72 Hz. These cards included an 8-bit or 24-bit Z-buffer and double buffering capabilities, which could be expanded through additional VSIMM or Z-buffer modules. The Turbo variants added a 24-bit off-screen pixmap buffer alongside the Z-buffer.
These accelerators were built around Digital's proprietary PixelStamp architecture, which originated from UNC's Pixel Planes and Carnegie Mellon's The 8 by 8 Display. This architecture incorporates a DMA engine connected to TURBOchannel, an Intel i860 processor-powered geometry engine equipped with SRAM, and a PixelStamp component consisting of STIC plus one or two STAMP ASICs responsible for rasterization and graphical processing. The final RGB output is stored within VSIMM-based framebuffers located on the module.
The PXG and PXG+ are double-width TURBOchannel cards, whereas PXG Turbo and PXG Turbo+ occupy triple-width slots. Models marked with "+" feature enhanced components (44 MHz i860 versus 40 MHz, along with faster ASIC clock speeds). The "Turbo" variants include an increased SRAM size of 256 KB and dual STAMP ASICs compared to the standard 128 KB SRAM and single ASIC. Entry-level models can be upgraded to mid-tier performance by adding VSIMMs and Z-buffer expansions.
Multimedia
Certain DECstation configurations supported video conferencing, superior audio output, and video input through TURBOchannel expansion cards and peripherals. Video input was facilitated by the DECvideo (also known as PIP (Picture-in-Picture) live-video-in) daughterboard, which connected to the TX framebuffer to accept NTSC, PAL, and SECAM video signals. When paired with a camera, microphone, and appropriate software, this setup enabled video conferencing capabilities.
Audio output was managed via the DECaudio TURBOchannel card, which incorporated two AMD 79C30A DSC chips for voice-grade audio and a Motorola 56001 DSP for high-fidelity sound processing. Although initially underutilized due to incomplete firmware support, later updates enabled full DSP functionality.
The DECspin application, introduced for DECstation 5000 and Personal DECstation 5000 systems, integrated DECmedia, DECvideo, and DECaudio hardware to provide videoconferencing services supporting up to six participants over LAN connections or through DECnet routers on remote links. In 1992, workstation pricing for this solution started at $2,995.
DECstation PCs
In addition to the DECstation series of workstations, Digital launched a line of DECstation-branded PC compatible computers powered by Intel x86 processors and operating on MS-DOS. These models, distinguished by three-digit numbers—DECstation 2xx, 3xx, and 4xx—featured Intel 80286, 80386, and 80486 CPUs, respectively. Production was handled by Tandy Corporation in the United States and Olivetti in Europe. Digital also provided a trade-in scheme aimed at customers who owned earlier non-PC-compatible Rainbow 100 systems.
The lineup of 80286 processor-based machines comprised:
- DECstation 210
- DECstation 220
- DECstation 212
- DECstation 212LP
Models equipped with the 80386 processor included:
- DECstation 316
- DECstation 316+
- DECstation 316sx
- DECstation 320
- DECstation 320+
- DECstation 320sx
- DECstation 325c
- DECstation 333c
The range featuring the 80486 processor consisted of:
- DECstation 420sx
- DECstation 425c
- DECstation 433T
- DECstation 433W
- DECstation 450dx2