PDP-8
| Industry | Computer hardware |
|---|---|
| Founded | 1957 |
| Founder | Ken Olsen, Harlan Anderson |
| Headquarters | Maynard, Massachusetts , United States |
| Products | PDP-8 series minicomputers, others |
Number of employees | 14000 (1975) |
| Website | en |
The PDP-8 series represents a line of 12-bit minicomputers developed by Digital Equipment Corporation (DEC). Introduced in 1965, it was the first minicomputer to be priced below $20,000, establishing a new standard for affordable minicomputers. Throughout its production, more than 50,000 units were sold.
Its architecture is an evolution of the innovative LINC design, incorporating a condensed yet enhanced version of the PDP-5 instruction set. To minimize manufacturing expenses, several standard operations were excluded and needed to be emulated through combinations of other instructions, which made programming more intricate.
Among its derivatives are the PDP-12, capable of executing software for both PDP-8 and LINC platforms, and the PDP-14, an industrial controller built as a ruggedized variant of the PDP-8. The PDP-11 succeeded this family with a richer instruction set and did not maintain backward compatibility.
Overview
The initial PDP-8 model, often referred to as the "Straight-8," debuted on March 22, 1965, with a price tag of $18,500. It employed diode–transistor logic implemented on flip chip cards housed within a compact chassis roughly the size of a small refrigerator. As the first computer sold for under $20,000, it quickly became the top-selling machine of its era. The following year saw the release of the PDP-8/S, available in both desktop and rack-mounted forms. Featuring a one-bit serial arithmetic logic unit (ALU), this version offered a smaller and more affordable design with entry-level models priced below $10,000—the first to reach this price point.
Later iterations such as the PDP-8/I, /L, /E, /F, /M, and /A reverted to faster, fully parallel architectures utilizing cost-efficient transistor–transistor logic (TTL) MSI technology. The majority of existing PDP-8 units originate from this generation. The PDP-8/E is particularly recognized for supporting an extensive variety of I/O peripherals. The final commercial variants introduced in 1979—the "CMOS-8s"—employed CMOS microprocessors but did not achieve commercial success due to pricing issues. Nonetheless, their low energy consumption made them well-suited for embedded military roles. These integrated circuits were marketed by Intersil as the Intersil 6100 family up until 1982.
Chief engineer Edson de Castro, who later established Data General, was responsible for designing the original PDP-8.
Architectural significance
The PDP-8 distinguished itself by combining affordability, straightforwardness, modularity, and meticulous engineering focused on delivering value. Its most profound contribution was democratizing computing by making it accessible to a broader range of customers and applications through low cost and mass production. It continues to serve as an important example of value-driven computer architecture.
However, its simplicity also resulted in programming challenges; tasks such as performing subtraction required manual implementation via two's complement arithmetic, and conditional branching was achieved through skip instructions. Some initiatives encountered failures due to limited memory or architectural shortcomings like difficult-to-debug recursive subroutines.
As prices for logic components and memory decreased over time, programming efficiency gained importance. Subsequent designs emphasized programming ease by incorporating larger and more user-friendly instruction sets. Eventually, most machine-level code was generated through compilers and report generators. The reduced instruction set computer (RISC) philosophy echoed the PDP-8’s minimalist instruction approach aimed at maximizing execution speed but employed longer instruction formats.
Description
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The PDP-8 architecture is a development derived from the PDP-5 and earlier 12-bit systems influenced by Seymour Cray’s CDC 160 minicomputer. It operates with 12-bit data words and arithmetic, supporting unsigned values from 0 to 4095 or signed numbers between −2048 and +2047, with software enabling multiple-precision calculations. A floating-point interpreter utilizing a 36-bit format was also available.
Its memory addressing scheme covers 12 bits, providing a fundamental core memory of 4,096 words (equivalent to 6 KiB), expandable through bank switching controlled by IOT instructions. The memory cycle time is 1.5 microseconds (approximately 0.667 MHz), which results in typical instruction execution speeds near 0.333 MIPS. Despite its modest cost, the PDP-8 delivers computational performance comparable to pricier contemporaries such as the IBM 1130 and IBM System/360 series, while facilitating simpler interfacing with peripheral devices.
Designed with applications like telecommunications and text processing in mind, the PDP-8 efficiently encodes two six-bit characters per word, compatible with teletypesetting codes widely used by news wire services.
Its instruction set comprises eight primary instructions identified by three-bit opcodes, augmented by assembler mnemonics that translate into OPR or IOT commands. The architecture exposes only three registers directly accessible to programmers: a 12-bit accumulator (AC), the program counter (PC), and a carry indicator known as the "link register" (L). Additional internal registers perform various functions to minimize hardware complexity and cost.
Input/output operations utilize a single shared interrupt line, an I/O bus for programmed I/O devices such as printers and paper tape readers, along with a DMA channel designed for higher-speed peripherals like CRT displays and disk drives.
To reduce expenses, the design employs inexpensive main memory for tasks often handled by costly flip-flop registers in other systems. Entry-level models depend on software routines for multiplication and division, whereas an optional Extended Arithmetic Element (EAE) offers hardware multiply/divide instructions using the MQ register for enhanced mathematical performance.
The PDP-8 emphasizes simplicity by eliminating superfluous features and sharing logic components to lower costs. Features like autoincrement, autoclear, and indirect addressing contribute to faster operation while conserving memory resources.
Early versions were priced below most commercial computers of their time and incorporated semi-automated wire-wrap technology for backplane assembly. The initial CPU design required 75 small modules alongside 25 double-sized modules from the R series Flip-Chip family.
Released in August 1966, the PDP-8/S model reduced logic gate count by employing a serial data path one bit wide for arithmetic processes, resulting in a compact breadbox-sized enclosure designed by Saul Dinman.
The PDP-8/E introduced enhanced capabilities using faster transistor–transistor logic integrated circuits and an improved core memory design. Its OMNIBUS architecture replaced wire-wrapped backplanes, enabling more economical system expansion.
Models
The PDP-8 series achieved total sales surpassing 300,000 units. Major models produced in this line include:
| Model | Description | Year Released | Price at Launch | Units Manufactured | Weight |
|---|---|---|---|---|---|
| PDP-8 | Utilized semi-discrete components alongside some hybrid integrated circuits; employed DTL logic. | 1965 | $18,000 | 1,450 | 250 pounds (110 kg) |
| LINC-8 | Operated in dual modes, capable of running either LINC or PDP-8 instructions. | 1966 | $38,500 | 142 | |
| PDP-8/S | A more affordable serial implementation. | 1966 | $10,000 | 1,024 | 84 pounds (38 kg) |
| PDP-8/I | First model to incorporate standard TTL integrated circuits. | 1968 | $12,800 | 3,698 | 250 pounds (110 kg) |
| PDP-8/L | A budget-friendly alternative to the PDP-8/I. | 1968 | $8,500 | 3,902 | 80 pounds (36 kg) |
| PDP-12 | Combined PDP-8/I with LINC instruction capabilities, succeeding the LINC-8. | 1969 | $27,900 | 755 | |
| PDP-8/E | Enhanced design featuring fewer yet larger circuit boards for improved efficiency. | 1970 | $6,500 | 90 pounds (41 kg) (average) | |
| PDP-8/F | Cost-reduced variant of the PDP-8/E. | 1972 | 57 pounds (26 kg) (average) | ||
| PDP-8/M | Original equipment manufacturer (OEM) version of the PDP-8/F with a modified front panel. | 1972 | $5,000 | 57 pounds (26 kg) (average) | |
| PDP-8/A | Featured single-board CPU enabled by LSI logic technology. | 1974 | $1,835 | ||
| Intersil 6100 | A microprocessor on a single chip compatible with the PDP-8 architecture (utilized in VT78). | 1975 | |||
| Harris 6120 | CMOS-based single-chip microprocessor compatible with the PDP-8 (used in DECmate word processors). | 1976 |
Recent implementations
Due to its relatively straightforward instruction set compared to contemporary architectures, the PDP-8 is extensively emulated. Hobbyists have reconstructed complete PDP-8 systems within single field-programmable gate array (FPGA) devices.
Various software emulators and open-source hardware re-creations are available, many capable of executing DEC’s original operating systems and diagnostic programs. These emulations typically replicate later-generation PDP-8 models with comprehensive peripheral support while utilizing only a small fraction of modern personal computer resources.
Input/output
Throughout its production span, the PDP-8's input/output systems underwent considerable development. Initial versions incorporated a front panel, a punched tape reader, and a Teleprinter printer often paired with a paper-tape punch. Subsequent enhancements introduced DECtape, RS-232 and current loop interfaces for simple terminals, as well as punched card readers and drum memory fixed-head disk drives. In later stages, adoption of floppy disk drives and moving-head cartridge-based hard disk drives became prevalent. Today’s enthusiasts have engineered standard PC-style Integrated Drive Electronics (IDE) hard disk adapters compatible with both physical and emulated PDP-8 machines.
Supported input/output configurations encompass:
- Dedicated I/O controller slots within the backplane
- "Negative" I/O bus utilizing negative voltage signaling
- "Positive" I/O bus employing TTL signaling
- The Omnibus backplane introduced in the PDP-8/E featuring undedicated system bus slots
A simplified direct memory access mechanism known as "three-cycle data break" requires processor intervention by integrating DMA control logic inside the CPU. This approach updates transfer address and word count registers across three memory cycles concurrent with data movement.
The "one-cycle data break," which accelerates DMA transfers by threefold through transferring only target data, gained traction with the advent of the PDP-8/E. This was facilitated by reduced electronic logic costs that allowed I/O devices to handle their own registers independently.
Programming environments
Initial PDP-8 models were delivered without any preloaded software; users had to input instructions manually using twelve toggle switches during startup, commonly loading a bootstrap loader from paper tape. The development of programs relied heavily on paper tape for both input and output.
Programming languages available on paper tape included DEC's FOCAL interpreter and a 4K FORTRAN compiler with runtime support.
Subsequent operating systems such as OS/8 and COS-310 offered conventional command-line interfaces equipped with editors and compilers for PAL-III assembly, FORTRAN, BASIC, and DIBOL.
More sophisticated systems were introduced, including real-time operating systems (RTS-8), multiuser commercial platforms (COS-300, COS-310), and single-user word-processing environments (WPS-8).
The TSS-8 time-sharing system enabled multiple users to connect via 110-baud terminals for tasks like editing, compiling, and debugging. Supported programming languages encompassed a tailored BASIC, subsets of FORTRAN and ALGOL, FOCAL, and PAL-D assembler.
A wealth of user-developed software was disseminated through DECUS, Digital Equipment Corporation’s User Society, often accompanied by complete source code and documentation.
Instruction set
The upper three bits (bits 0–2) within the 12-bit instruction word specify the opcode. For six instructions involving memory access, bits 5–11 provide a seven-bit address. Bit 4 controls whether the address is formed by combining with the high five bits of the program counter (PC), thus addressing within the current 128-word memory page; if this bit is cleared, zeroes are used instead, addressing the first 128 words of memory. Bit 3 serves as an indirection flag; when set, the address refers to a 12-bit memory location that contains the actual effective address, permitting operands anywhere in memory at the cost of an additional word fetch. The JMP instruction follows this format but does not access a memory word unless indirection is active.
| 0 | 2 | 3 | 4 | 5 | 11 | ||||||
| Operation | I | Z | Offset | ||||||||
- Memory paging
This instruction structure segments the total 4,096-word memory into pages of 128 words each; bit 4 selects between the current page or page zero (addresses ranging from 0000 to 0177 octal). Page zero holds particular importance for storing variables accessible from any page and for interrupt service routines that begin at address 0000. Addresses from 0010 to 0017 increment automatically before any indirect addressing occurs, facilitating efficient pointer manipulation.
Assemblers strategically position constants and cross-page jump targets within these pages to enhance efficiency. Reducing page crossings was critical since references beyond the current page necessitate an additional word, which affects both code size and execution speed. Programmers frequently arranged code near the end of pages to allow smooth transitions as the program counter advanced.
Fundamental Instructions
- 000 – AND – Perform a bitwise AND between the memory operand and the accumulator (AC).
- 001 – TAD – Add the two's complement of the memory operand to the combined <L,AC> register (a 12-bit signed value including carry).
- 010 – ISZ – Increase the memory operand by one and skip the following instruction if the result is zero.
- 011 – DCA – Store the content of AC into the memory operand and then clear AC.
- 100 – JMS – Jump to a subroutine, saving the return address in the first word of that subroutine.
- 101 – JMP – Unconditional jump to the specified address.
- 110 – IOT – Execute Input/Output Transfer instructions.
- 111 – OPR – Carry out microcoded operations.
IOT (Input/Output Transfer) Instructions
The PDP-8 CPU establishes a general structure for IOT instructions, with most details defined by each specific I/O device.
| 0 | 2 | 3 | 8 | 9 | 11 | ||||||
| 6=IOT | Device | Function | |||||||||
- Device
Bits 3 through 8 select an I/O device. Common device addresses include:
- 00: Processor control (detailed below).
- 01: High-speed paper tape reader.
- 02: High-speed paper tape punch.
- 03: Console keyboard and low-speed paper tape reader.
- 04: Console printer and low-speed paper tape punch.
Instructions targeting device 0 affect overall processor behavior, such as ION (6001) which enables interrupts, or IOFF (6002) which disables them.
- Function
Bits 9 to 11 define specific functions for each device. For simpler devices, these bits have consistent meanings:
- Bit 11 causes skipping of the next instruction if the device signals readiness.
- Bit 10 clears the accumulator (AC).
- Bit 9 transfers a word between AC and the device, initiates I/O, and resets the device's ready flag.
These function bits execute sequentially, allowing combinations of operations. More complex devices like disk drives interpret these bits to provide up to eight unique device-specific functions.
OPR (Operate) Instructions
OPR instructions manage numerous tasks, including conditional operations, without directly addressing memory locations. Conditional execution is implemented by skipping the subsequent instruction, often a JMP.
The term "microcoded" in OPR indicates that individual bits within the instruction activate distinct operations, enabling multiple actions in a single cycle by combining bits logically. Assemblers merge mnemonics using logical OR to produce the final instruction word. Many I/O devices also utilize microcoded IOT instructions.
The execution order of these actions is fixed to maximize the effectiveness of combined operations.
OPR instructions are categorized into Groups identified by bits 3, 8, and 11, ensuring that actions from different groups are not mixed within a single instruction.
A universal feature across all groups is bit 4 (CLA), which clears the accumulator when set.
Group 1
00 01 02 03 04 05 06 07 08 09 10 11
___________________________________
| 1| 1| 1| 0| | | | | | | | |
|__|__|__|__|__|__|__|__|__|__|__|__|
|CLA CMA RAR BSW
CLL CML RAL IAC
Execution order: 1 1 2 2 4 4 4 3
- 7200 – CLA – Clear accumulator contents
- 7100 – CLL – Clear Link bit
- 7040 – CMA – Complement accumulator bits (ones' complement)
- 7020 – CML – Complement Link bit
- 7001 – IAC – Increment combined <L,AC> register
- 7010 – RAR – Rotate combined <L,AC> one bit right
- 7004 – RAL – Rotate combined <L,AC> one bit left
- 7012 – RTR – Rotate combined <L,AC> two bits right
- 7006 – RTL – Rotate combined <L,AC> two bits left
- 7002 – BSW – Swap two six-bit halves of AC (PDP-8/e and later)
Operations are designed to be combined efficiently. For instance, CLA, CLL, and IAC together clear both AC and Link before incrementing AC to set it to one. Adding RAL (CLA CLL IAC RAL) clears, increments, then rotates left once, resulting in AC being set to two. This mechanism facilitates loading small integer constants with a single instruction.
The combination CMA followed by IAC (abbreviated CIA) yields the two's complement negation of AC. Since subtraction is not directly supported, calculating differences involves negating the subtrahend before performing addition via TAD.
A Group 1 OPR instruction with no bits set in its microprogram does nothing and functions as a no-operation (NOP).
Group 2, Or Group
00 01 02 03 04 05 06 07 08 09 10 11
___________________________________
| 1| 1| 1| 1| | | | |0| | |0|
|__|__|__|__|__|__|__|__|__|___|___|__|
|CLA SZA OSR
SMA SNL HLT
2 1 1 1 3 3
- 7600 – CLA – Clear the AC register
- 7500 – SMA – Skip if AC is less than zero (or group)
- 7440 – SZA – Skip when AC equals zero (or group)
- 7420 – SNL – Skip if L is not zero (or group)
- 7404 – OSR – Perform a logical OR between front-panel switches and AC
- 7402 – HLT – Halt execution
Among these bits, three (CLA, OSR, HLT) initiate specific operations when enabled, while the other three (SMA, SZA, SNL) define skip conditions. The instruction skips if any of the specified conditions hold true; for instance, the "SMA SZA" combination (opcode 7540) causes a skip if AC is less than or equal to zero.
A Group 2 OPR command with no bits activated functions as a No-Operation.
Group 2, And Group
00 01 02 03 04 05 06 07 08 09 10 11
___________________________________
|1|1|1|1| | | | |1| | |0|
|__|__|__|__|__|__|__|__|__|__|__|__|
|CLA SNA OSR
SPA SZL HLT
2 1 1 1 3 2
- 7410 – SKP – Always skip unconditionally
- 7610 – CLA – Clear the AC register
- 7510 – SPA – Skip if AC is zero or positive (and group)
- 7450 – SNA – Skip when AC is not zero (and group)
- 7430 – SZL – Skip if L equals zero (and group)
When bit 8 is set, the logic for skip conditions is reversed; skipping does not occur if any of the or-group conditions are true. Applying De Morgan's laws, this means a skip happens only when every inverted condition holds. For example, "SPA SNA" (opcode 7550) skips only if AC is greater than zero. If none of bits 5 through 7 are active, skipping occurs unconditionally.
The operation bits (CLA, OSR, HLT) remain unaffected by bit 8’s inversion.
Group 3
Unused combinations of OPR bits designate a third group of microcoded functions primarily manipulating the MQ (Multiplier/Quotient) register. The MQ and extended arithmetic element (EAE) instructions are optional features available with the EAE extension.
00 01 02 03 04 05 06 07 08 09 10 11
___________________________________
| 1| 1| 1| 1| | | | | | | | 1|
|__|__|__|__|__|__|__|__|__|__|__|__|
|CLA SCA \_ _/
| MQA MQL CODE
1* 2 2 2 3
Key instructions include:
- 7601 – CLA – Clear AC register
- 7501 – MQA – Logical OR MQ into AC
- 7441 – SCA – Load step counter into AC
- 7421 – MQL – Move AC contents to MQ and clear AC
- 7621 – CAM – Combination of CLA and MQL clears both AC and MQ
Typical bit combinations such as CLA + MQA result in transferring MQ into AC; while MQA + MQL exchanges the values between these two registers.
Multiply and divide commands encompass:
- 7401 – No operation
- 7403 – SCL – Load step counter immediately following instruction (PDP-8/I and later models)
- 7405 – MUY – Multiply operation
- 7407 – DVI – Divide operation
- 7411 – NMI – Normalize operation
- 7413 – SHL – Shift left with immediate word following instruction
- 7415 – ASR – Arithmetic shift right
- 7417 – LSR – Logical shift right
Memory control
The initial PDP-8 featured 12-bit addressing, enabling direct access to 4,096 words (6 kB). As software demands increased and memory became more affordable, expanding this limit was necessary.
The Memory Extension Controller expanded the addressable memory capacity by a factor of eight, reaching 32,768 words (32K), striking a balance between cost efficiency and system performance. Memory was segmented into 4K-word fields. Two three-bit registers—DF (Data Field) and IF (Instruction Field)—were used to select the appropriate field for data and instruction accesses. This extended the address space to 15 bits while maintaining compatibility with earlier models.
Instructions within the 6200–6277 range control the DF and IF registers, enabling programs to switch memory fields on the fly. For example, the CDF instruction sets the data field, while CIF sets the instruction field; both can be configured simultaneously. The effect of CIF is delayed until the next jump instruction to prevent interrupting program execution flow.
Although managing multiple memory fields introduced additional complexity compared to flat addressing schemes such as the Intel 8086’s segmented architecture, this approach preserved software compatibility and upheld the PDP-8’s architectural consistency.
This expanded memory framework supported applications like multi-user timesharing systems by assigning distinct fields to individual users. For instance, FOCAL could be modified to utilize a second field for user programs and data beyond its usual single-field restriction.
- Virtualization
Beginning with the PDP-8/E model, enhancements to the Memory Extension Controller facilitated machine virtualization. A virtual machine manager could intercept all I/O instructions—including those manipulating DF and IF—allowing multiple programs to securely share hardware resources.
Additional I/O instructions were introduced to save and restore DF and IF states during traps. However, since CIF effects are postponed until a jump instruction executes, the virtual machine manager must emulate instructions occurring between CIF and that jump when trapping happens—this represents a minor performance compromise in exchange for virtualization support.
By the time of the PDP-8/A generation, falling memory prices justified addressing beyond eight fields. New instructions allowed field numbers to be specified in the AC register rather than being hard-coded in instructions. Despite this capability, limited software adoption occurred due to the platform’s waning popularity.
Examples
The examples below illustrate PDP-8 assembly language code as written for the PAL-III assembler.
Comparing two numbers
This snippet compares two values stored at OPD1 and OPD2:
/ Compare values at OPD1 and OPD2
CLA CLL / Clear AC and link
TAD OPD1 / Load first value into AC
CIA / Complement and increment AC (negate)
TAD OPD2 / AC = OPD2 - OPD1; link set if overflow
SZL / Skip next if link is clear
JMP OP2GT / Jump if OPD2 ≥ OPD1; otherwise continue
This example highlights how PDP-8 programming centers on low-level operations, with conditional jumps implemented via skip instructions that invert logical conditions.
Logical OR
Since PDP-8 lacks a dedicated logical OR instruction, this code applies De Morgan's laws using a temporary storage location TMP to compute OPD1 OR OPD2, leaving the final result in AC:
CLA / Clear AC
TAD OPD1 / Load first operand
CMA / Complement AC
DCA TMP / Store complemented value in TMP
TAD OPD2 / Load second operand
CMA / Complement AC again
AND TMP / AC = NOT(OPD2) AND NOT(OPD1)
CMA / Complement result to obtain (OPD1 OR OPD2)
String output
Presented below is a full PDP-8 assembly program that prints "Hello, world!" on the teleprinter:
*10 / Initialize origin at 10 for auto-increment registers
STPTR, STRNG-1 / Pointer referencing the start of the string
*200 / Program start address
HELLO, CLA CLL / Clear accumulator and link bit
TAD I Z STPTR / Indirectly load the next character
SNA / Skip next instruction if accumulator is non-zero (string not ended)
HLT / Halt execution if zero (end of string reached)
TLS / Transmit character to teleprinter
TSF / Skip if teleprinter is ready
JMP .-1 / Wait loop until teleprinter ready
JMP HELLO / Repeat for subsequent characters
STRNG, 310 / H
345 / e
354 / l
354 / l
357 / o
254 / ,
240 / (space)
367 / w
357 / o
362 / r
354 / l
344 / d
241 / !
0 / Null terminator marking end of string
$HELLO / Default program terminator
Subroutines
The PDP-8 CPU does not include a dedicated stack mechanism for preserving registers or processor state during subroutine invocations or interrupt handling. Instead, the JMS instruction saves the updated program counter—pointing just beyond the JMS call location—at the effective address and branches to that address plus one. To return from the subroutine, an indirect JMP through this stored word is performed.
As an illustration, a "Hello, World!" example employing a subroutine shows how JMS modifies the memory location OUT1:
*10 / Set assembly origin to address 10,
STPTR, STRNG-1 / Auto-increment register (addresses 10-17)
*200 / Program load address
LOOP, TAD I STPTR / Pre-increment memory location 10; fetch next character
SNA / Skip next instruction if accumulator is non-zero
HLT / Halt when end of message detected
JMS OUT1 / Call subroutine to output character
JMP LOOP / Loop back for additional characters
OUT1, 0 / Placeholder replaced by caller’s updated PC
TSF / Skip if teleprinter ready flag set
JMP .-1 / Wait until printer is ready
TLS / Send character stored in accumulator to teleprinter
CLA CLL / Clear accumulator and link bit before return
JMP I OUT1 / Return control indirectly to caller
STRNG, "H / Message encoded in sixbit format:
"e /
"l /
"l /
"o /
", /
" /
"w /
"o /
"r /
"l /
"d /
"! /
015 /
012 /
0 / Null terminator marking string end
Because JMS stores the return address immediately preceding the subroutine code itself, it inherently disallows reentrant or recursive calls without additional programming techniques. This approach also complicates usage with ROM, since return addresses are written into code space. Programs designed for ROM typically employ one of these strategies:
- Copy their code into writable memory before execution begins,
- Utilize specialized ROM modules that include limited writable bits accessed via a thirteenth flag bit per ROM word,
- Eschew subroutines altogether or substitute JMS with routines that save return addresses in writable memory locations, such as:
JUMPL, DCA TEMP / Store accumulator content into TEMP variable
TAD JUMPL+3 / Load hardcoded return address into accumulator
JMP SUBRO / Jump to subroutine which manages return flow
The use of JMS complicates debugging efforts because recursive invocations overwrite saved return addresses, causing infinite loops. Additionally, incorrect subroutine entry points may overwrite subroutine instructions with invalid return addresses, resulting in failures during subsequent correct calls.
Software stack
While the PDP-8 does not possess a hardware-based stack, it is feasible to create stack functionality through software. Below are basic PUSH and POP routines, presented without safeguards against overflow or underflow conditions:
*100 /Enable access to routines for subsequent example
PUSH, 0
DCA DATA
CLA CMA /Load -1 into accumulator
TAD SP
DCA SP
TAD DATA
DCA I SP
JMP I PUSH /Return from subroutine
POP, 0
CLA CLL
TAD I SP
ISZ SP
JMP I POP
DATA, 0
SP, 0
The following "Hello World" demonstration utilizes this software stack alongside an "OUT" subroutine:
*200
MAIN, CLA CLL /Initialize pointer to message
TAD (MESSG /Load address of message start (literal)
DCA SP
LOOP, JMS POP
SNA /Halt if zero character encountered
HLT
JMS OUT /Send character to output device
JMP LOOP
MESSG, "H
"e
"l
"l
"o
",
"
"w
"o
"r
"l
"d
"!
015
012
0
OUT, 0 /Replaced by caller's PC on call
TSF /Skip if printer ready flag set
JMP .-1 /Wait loop until ready
TLS /Transmit AC contents to printer
CLA CLL /Clear AC and Link for next character
JMP I OUT /Return control to caller
Linked list
Linked list operations can also be programmed on the PDP-8, as illustrated by the following subroutine:
GETN, 0 /Fetch number referenced by pointer and advance it
CLA CLL /Clear accumulator and link bit
TAD I PTR /Retrieve value pointed to by PTR
DCA TEMP /Store retrieved number temporarily
ISZ PTR /Increment pointer address
TAD I PTR /Load new number pointed to by updated PTR
DCA PTR /Update pointer variable with new address
JMP I GETN /Return from subroutine
PTR, 0
TEMP, 0
Interrupts
The PDP-8 features a single interrupt line connected via its I/O bus. Upon receiving an interrupt signal, the processor disables additional interrupts and initiates a JMS call to address 0000. Because writing reentrant interrupt handlers is complex, nested interrupts are typically avoided; each interrupt routine completes fully before interrupts are re-enabled and control returns using JMP I 0.
With only one interrupt input line, the processor cannot directly identify which device triggered the interrupt. Instead, the interrupt handler sequentially polls each active peripheral through a skip chain—a series of conditional skip instructions. The priority of devices is determined by their position in this chain: devices checked earlier receive service before those later in the sequence. Occasionally, an interrupt may occur when no device actually requires attention.
Books
A comprehensive engineering text from the 1980s, The Art of Digital Design by David Winkel and Franklin Prosser, presents a detailed multi-chapter case study on constructing a computer compatible with the PDP-8/I. It thoroughly explains the role of each component. Although it does not represent a production design—relying instead on modern SSI and MSI logic chips and solid-state memory rather than core memory—the work provides an in-depth understanding of how such a computer functions.
Unlicensed replicas
The Soviet Union created the Saratov-1 and Saratov-2 minicomputers, which were imitations of the PDP-8 and PDP-8/E, respectively.
During the 1970s and 1980s, Bulgaria developed the IZOT-0310, a device modeled after the PDP-8L.
In Cuba, the Instituto Central de Investigación Digital (ICID), currently known as COMBIOMED, produced the CID-201 series of minicomputers in the 1970s. These machines partially replicated the designs of the PDP-8/S and PDP-8/L models.
References
- C. Gordon Bell and Allen Newell, 1971, Computer Structures: Readings and Examples, McGraw-Hill Book Company, New York. Chapter 5 titled The DEC PDP-8, pages 120–136. Provides sufficient detail for an electrical engineer to construct one (assuming component availability).
External links
- pdp-8 Documentation: The Small Computer Handbook (1966 Edition), Sections 1 and 2 and additional resources from Simon Fraser University
- PDP-8 Frequently Asked Questions Internet FAQ Archives
- The Digital Equipment Corporation PDP-8, 1965 Computer History Collection at the Smithsonian
- Digital Equipment Corporation's PDP-8 Steve Gibson’s detailed overview of PDP-8 functionality and programming