Data General Nova
| Company type | Private |
|---|---|
| Industry | Computer hardware |
| Founded | April 15, 1968 in the United States |
| Founder | Edson de Castro, Henry Burkhardt III, Richard Sogge |
| Headquarters | United States |
| Products | Nova series minicomputers, including Nova, SuperNOVA, Nova 800, Nova 1200, microNOVA |
The Nova series consists of 16-bit minicomputers developed by the American firm Data General. Achieving widespread popularity throughout the 1970s, the Nova lineup sold in the tens of thousands.
The initial "Nova" was introduced in 1969, featuring a compact 3U rack-mount enclosure and providing adequate processing power for a variety of fundamental tasks. It became especially favored within scientific research laboratories around the globe. In 1970, the SuperNOVA model was launched, delivering approximately four times the performance and holding the title of fastest minicomputer for several subsequent years.
As integrated circuit technology rapidly progressed, Data General extended the Nova product family over a five-year span with versions such as the 800, 1200, Nova 2, Nova 3, and Nova 4. The microNOVA, a single-chip iteration introduced in 1977, experienced limited commercial success due to shifting market preferences toward emerging microprocessor designs. Similarly, Fairchild Semiconductor's microprocessor adaptation from that year, the Fairchild 9440, failed to gain significant traction.
Ultimately, the Nova range was replaced by the Data General Eclipse, which preserved much of the original architecture while incorporating virtual memory and capabilities tailored for contemporary operating system environments. This platform evolved into the 32-bit Eclipse MV series during the 1980s.
Edson de Castro and the PDP-X
Edson de Castro served as Product Manager for Digital Equipment Corporation’s (DEC) groundbreaking PDP-8, a 12-bit minicomputer, and led development of its successor, the PDP-8/I, which integrated early forms of integrated circuit technology.
During work on the PDP-8/I, de Castro noticed improvements in circuit board manufacturing that allowed for fully automated assembly on larger boards. Despite this, DEC favored smaller "flip-chip" boards because they simplified troubleshooting, even though larger boards offered potential advantages.
The industry’s adoption of ASCII in 1967 encouraged a move toward designs with 16-bit word lengths. This inspired de Castro to conceive a 16-bit minicomputer CPU implemented on a single 15-inch board.
In 1967, de Castro launched the "PDP-X" initiative aimed at creating a unified architecture spanning 8-, 16-, and 32-bit systems. Although detailed architectural plans were developed, DEC CEO Ken Olsen terminated the project in 1968 due to skepticism about its superiority over existing products.
Design
After PDP-X was discontinued, de Castro contemplated departing DEC to build a novel system independently. Joined by engineers Pat Green and Richard Sogge along with software engineer Henry Burkhardt III, the team set out to develop a commercially viable machine rapidly, initially focusing on an 8-bit design to keep production costs low.
They collaborated with Herbert Richman from Fairchild Semiconductor, whose company was advancing in the TTL space through its 9300 series chips capable of integrating up to 96 gates per chip. These integrated circuits allowed key CPU components such as the arithmetic logic unit (ALU) to be consolidated onto fewer chips, facilitating expansion from an 8-bit to a 16-bit architecture.
While CPU circuitry grew from one to two printed circuit boards, it remained considerably more affordable and powerful than the PDP-8/I. A third board managed input/output operations, and a fourth typically housed 4 kB of random-access memory. The entire four-board assembly was contained within a single rackmount chassis.
The boards interconnected via a printed circuit backplane, which significantly reduced manual wiring and enabled automated assembly processes—lowering costs compared to the PDP-8/I’s numerous small boards that required manual wiring. This approach also improved reliability, making it attractive for industrial and laboratory applications.
The design employed a straightforward load–store architecture, which later influenced RISC architectures. To offset limited addressing modes, the CPU incorporated four general-purpose accumulators, unlike comparable budget systems that typically had only one register—enhancing both performance and versatility.
Introduction
Towards the end of 1967, Richman connected the team with New York attorney Fred Adler, who successfully obtained initial funding from a Boston-based venture capital group. This financial backing included seed money plus additional funds allocated for production. On April 15, 1968, de Castro, Burkhart, and Sogge departed from DEC to establish Data General (DG). Green opted not to join due to the associated risks, while Richman became involved later once the product was operational.
The development of the first system spanned approximately nine months, with initial sales commencing in November 1968. At the postponed Fall Joint Computer Conference in December, they demonstrated a functioning unit running Spacewar!. The Nova was officially introduced in 1969, priced at , and promoted as "the best small computer in the world." The entry-level version required additional memory—commonly () of core RAM—to be functional, elevating the total cost to around . This pricing remained competitive compared to the PDP-8/I, which was priced at but came with less memory.
The inaugural sale was made to a university in Texas; although delivery of the first unit was delayed by an airline strike, a second unit was shipped promptly after the strike ended. Eventually, the original unit also arrived.
The Nova rapidly gained market acceptance, reaching its 100th sale within six months and its 500th within fifteen months. With successive model releases, sales momentum increased significantly, culminating in annual revenues of by 1975.
SuperNOVA
Ken Olsen had forecasted DG’s failure; however, the launch of the Nova proved otherwise. By this period, competitors were developing 16-bit architectures, which Olsen perceived as a challenge to DEC's existing 18-bit and 12-bit product lines. This spurred DEC to introduce the PDP-11 in 1970—a sophisticated design intended to compete directly with the Nova.
Shortly after shipping the Nova, DG recruited designer Larry Seligman in 1970 to engineer an enhanced system. Two pivotal technological breakthroughs facilitated this: Signetics' release of the 8260 4-bit integrated circuit significantly reduced chip count by a factor of three, and Intel's advancements in semiconductor memory provided faster alternatives to traditional core memory.
Seligman’s architecture capitalized on these innovations by expanding the ALU to a full 16-bit width across two circuit boards. This allowed single-cycle execution of arithmetic and logic operations, resulting in performance approximately four times that of the original Nova. Additionally, newer smaller core memory improved cycle time from 1,200 ns down to 800 ns—a further improvement by one-third. Performance gains were even more pronounced with optional read-only memory capable of accessing data in just 300 ns.
Released in 1970 under the name SuperNOVA, this system initially employed core memory but was engineered to take advantage of faster semiconductor memories introduced later as the SuperNOVA SC. Operating at a cycle time of 300 ns (3.3 MHz), it held the distinction of being the fastest minicomputer available for several years. Nevertheless, early semiconductor memories were expensive and generated considerable heat, which limited their widespread usage.
1200 and 800
In 1968, Fairchild showcased its Micromatrix gate array technology through the 4711—a prototype single-chip 4-bit ALU. While costly and not intended for mass production, Signetics’ introduction of the 8260 in 1969 spurred Texas Instruments and Fairchild to launch their own 4-bit ALUs in 1970: specifically the 74181 and 9341 models. These designs incorporated all standard logic functions while reducing chip count.
This development inspired Data General (DG) to create a new CPU architecture utilizing these integrated circuits, enabling a single-card CPU suitable for either the basic Nova or SuperNOVA systems. Their modular chassis design allowed customers to upgrade by swapping out CPU boards, facilitating scalable investments.
Ron Gruner joined DG after proactively reaching out and assumed responsibility for developing a cost-effective model, while Edson de Castro concentrated on a high-performance alternative.
Gruner's low-cost Nova 1200, launched in 1970 and named after its use of the original Nova’s 1,200 ns core memory cycle time, featured a 4-bit ALU implemented with a single 74181 chip—essentially repackaging the original Nova design. Following this, Seligman’s four-ALU SuperNOVA debuted in 1971 as the Nova 800, introducing an ironic naming convention where the lower-numbered model delivered superior performance. Both models were offered with various chassis options: the 1200 included seven slots; the 1210 had four slots; and the 1220 provided fourteen slots.
Later Versions
By this stage, the PDP-11 was equipped with a more comprehensive instruction set architecture compared to the Nova's more basic design. As improvements in integrated circuit cost-efficiency reduced the advantages of simplified instruction sets, Seligman spearheaded the creation of a new system compatible with the Nova but providing expanded functionality. This effort led to the development of the Data General Eclipse series, which enabled tailoring instruction sets for either scientific or data processing needs, effectively competing with the PDP-11 in premium market segments.
At the same time, speculation about DEC’s forthcoming 32-bit system prompted Data General to launch the Fountainhead Project under Gruner’s guidance. To better handle its complexity, development was moved to Research Triangle Park, North Carolina. Nevertheless, due to increasing intricacies, this initiative was ultimately discontinued.
Concurrently, progress on the Nova family continued alongside these ventures.
840
Introduced in 1973, the 840 incorporated a paged memory architecture supporting up to 17-bit addressing and included an index offset feature to access an expanded memory space of 128 kwords. Accommodating this memory capacity required considerable physical space; hence, the 840 was housed in a sizable 14-slot chassis.
Nova 2
Also launched in 1973, the Nova 2 streamlined previous designs by utilizing higher-density chips to reduce CPU footprint. In contrast to the SuperNOVA’s three large 15×15" circuit boards, the Nova 2 combined both CPU and memory onto a single board. It employed ROM to store boot code, which was transferred into core memory during program initialization. The model was offered in four-slot ("2/4"), seven-slot, and ten-slot ("2/10") configurations.
Nova 3
The Nova 3 (1975) introduced two additional registers dedicated to stack management and upgraded its processor using TTL components for improved speed. It came in two variants: a four-slot version (Nova 3/4) and a twelve-slot version (Nova 3/12).
Nova 4
Although Data General had initially intended to phase out the Nova line in favor of Eclipse systems, persistent demand led to the release of the Nova 4 in 1978. Built around four AMD Am2901 bit-slice ALUs, this model was designed to function as either a Nova 4 or an Eclipse S/140 by modifying microcode. An optional floating-point co-processor could be installed in a separate slot. Memory addressing utilized bank switching to support up to 128 kwords. Unlike earlier iterations, the Nova 4 eliminated the front panel console, instead relying on ROM-based machine code that allowed terminal emulation of a console interface.
The Nova 4 came in three versions: Nova 4/C (a single-board system with either 16 or 32 kwords of memory), Nova 4/S, and Nova 4/X (both featuring separate memory boards). The Nova 4/X included an active on-board memory management unit (MMU) capable of handling up to 128 kwords; although present on the Nova 4/S, its MMU was disabled via firmware. Both the 4/S and 4/X models incorporated a prefetch unit that could retrieve up to eleven instructions ahead, enhancing overall performance.
microNOVA
Data General created the microNOVA line as single-chip implementations of the Nova processor. To fit within a compact 40-pin dual in-line package (DIP), both the address bus and data bus shared sixteen pins, necessitating two cycles per memory operation and resulting in half the speed of the original Nova.
The initial chip, named mN601 (1977), was marketed variously as a CPU, a chipset for custom-built computers, a single-board computer with 4 kB RAM, and an entry-level Nova variant. Its successor, the mN602 (1979), integrated the chipset into one VLSI chip and powered systems such as the microNOVA MP/100 and larger MP/200 models.
Subsequently, Data General bundled the microNOVA with a monitor and dual floppy disk drives under the name Enterprise, released in 1981 running RDOS. However, these products were overshadowed by the concurrent launch of the IBM PC.
Legacy
The Nova played a significant role in shaping early personal computing devices such as the Xerox Alto (1973) and the Apple I (1976), and it also served as the foundation for the Computervision CGP graphics processors. Its distinctive front panel design influenced the development of the Altair 8800 (1975).
Leveraging the Nova's achievements, Data General launched faster systems including the Eclipse series, which featured an expanded instruction set, and the 32-bit MV-series intended to compete with DEC's VAX. The creation of the MV-series was famously documented in Tracy Kidder's The Soul of a New Machine. Eventually, Data General shifted focus towards Intel-based servers and storage products before being acquired by EMC.
A committed international community remains active in restoring and maintaining original 16-bit Data General machines.
Processor design
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Unlike the PDP-8, the Nova adopted a load–store architecture featuring four 16-bit accumulator registers, with two (registers 2 and 3) serving as index registers. It included a 15-bit program counter alongside a single-bit carry flag. Addressing modes centered on current plus zero page addressing, although it did not incorporate a stack register—this functionality was added with dedicated hardware memory in later Eclipse models.
The initial Nova versions performed arithmetic operations serially in 4-bit chunks using a single 74181 bitslice ALU. Within approximately one year, this was enhanced to a full 16-bit parallel arithmetic unit composed of four 74181 ALUs, referred to as the SuperNova. Later iterations integrated a stack unit along with built-in multiply and divide hardware.
The Nova 4 / Eclipse S/140 model utilized four AMD 2901 bit-slice ALUs controlled by microcode stored in ROM and marked the first Nova designed solely for DRAM main memory, discontinuing support for magnetic-core memory.
Memory and I/O
The minimum addressable unit of memory was a 16-bit word, with no support for byte-level addressing. Initial versions typically included 8K words of magnetic-core memory as a nearly essential upgrade, which increased the system price to $7,995.
This core memory module consisted of four groups, each containing four banks, with every bank holding two 64x64 core arrays, amounting to a total of 131,072 bits or 8,192 words (each 16 bits). The core was mounted on a compact "board-on-a-board" measuring 5.25" by 6.125", surrounded by driver circuitry, all assembled on a standard 15 x 15 inch board. External expansion allowed systems to grow up to 32K words of this RAM. Semiconductor ROM options were also available, allowing configurations without RAM that were favored in industrial settings. Original Nova models operated at approximately 200 kHz; meanwhile, the SuperNova variant supported clock speeds up to 3 MHz using specialized semiconductor main memory.
The uniform backplane design and standardized I/O signals facilitated seamless integration with programmed I/O and Data Channel peripherals, making device connections more straightforward compared to rival systems. Additionally, the Nova's backplane featured wire wrap pins for custom or specialized connector applications.
Programming model
The Nova’s instruction set was divided into three main groups: register-to-register operations, memory referencing instructions, and input/output commands, each fitting within a single word. Register instructions were designed to be bit-efficient and resembled RISC principles, supporting tests, bit shifts, and conditional instruction skipping. Optional hardware enhancements included integer multiply/divide units, floating-point units for single and double precision calculations, and memory management capabilities.
Early Nova units came with a BASIC interpreter stored on punched tape. Over time, Data General broadened the software ecosystem by adding languages such as FORTRAN IV, ALGOL, Extended BASIC, Business Basic, Interactive COBOL, and assemblers under consistent operating systems. Third-party developers and users further contributed languages including Forth, Lisp, BCPL, C, various ALGOL dialects, as well as proprietary versions of COBOL and BASIC.
Instruction set
The following instructions represent the core set implemented across all Nova processors. Certain models introduced additional instructions or optional hardware provided extra capabilities.
Arithmetic instructions
Arithmetic operations were performed exclusively between accumulators. For two-operand instructions, one operand came from the source accumulator and the other from the destination accumulator; results were stored in the destination accumulator. Single-operand instructions operated on the source register and replaced the destination register’s content. Source and destination accumulators could be identical in single-operand cases.
Each arithmetic instruction incorporated a "no-load" flag that prevented storing the result in the destination register—useful for testing without modifying data. In assembly language syntax, prefixing with '#' activated this flag.
The processor maintained a carry bit reflecting any carry out from the most significant bit after an operation. This carry bit could be preset before execution through a two-bit field allowing it to be set, cleared, or toggled. Assembly options included: 'O' to set carry, 'Z' to clear it, 'C' to complement it, or leaving it unchanged. When combined with the no-load option, the carry influenced calculations but was not updated afterward.
A two-bit field controlled shift operations applied before loading results: single-bit circular shifts left or right or byte swapping. Shifts involved a 17-bit circular rotation encompassing the carry bit; byte swaps left the carry unaffected. Assembly letters used were: 'L' for left shift, 'R' for right shift, 'S' for swapping bytes, or none.
A three-bit field specified conditional tests on results that could cause skipping of the next instruction if true. Assembly language indicated these tests as a third operand:
- SZR — skip if result equals zero
- SNR — skip if result is nonzero
- SZC — skip if carry equals zero
- SNC — skip if carry is nonzero
- SBN — skip if both carry and result are nonzero
- SEZ — skip if either carry or result is zero
- SKP — always skip next instruction
- None — never skip
The arithmetic instruction set included:
- MOV — copy source accumulator to destination
- COM — store bitwise complement of source into destination
- ADD — add source accumulator to destination
- ADC — add bitwise complement of source to destination
- NEG — negate source accumulator into destination
- SUB — subtract source from destination
- INC — increment source by one into destination
- AND — perform bitwise AND between accumulators into destination
Example demonstrating all options:
This example clears the carry flag; adds AC2 to AC0; applies a right circular shift to the result; tests whether the carry is set and skips the subsequent instruction if true; finally discards the result after testing. This sequence effectively sums two values while checking if the outcome is odd or even.
Memory reference instructions
The Nova instruction set comprised commands for transferring data between memory and accumulators, two control transfer instructions, and two memory test operations. Every memory reference instruction contained an eight-bit address portion along with a two-bit field specifying the memory addressing mode. The four addressing modes were defined as follows:
- Mode 0 — absolute addressing: the address field, zero-padded, directly specifies the target location.
- Mode 1 — relative addressing: the sign-extended address field is added to the current program counter value.
- Mode 2 — indexed addressing: the sign-extended address is combined with the contents of accumulator 2.
- Mode 3 — indexed addressing: the sign-extended address is added to accumulator 3.
Absolute addressing (Mode 0) could only access the initial 256 memory words, commonly known as "page zero." Despite its limited range, page zero was crucial since only addresses within this page could be accessed directly without employing accumulators as index registers. Assembly directives allowed placement of code and data either in page zero or in standard memory. Subsequent Nova versions introduced instructions with extended addressing capabilities to bypass page zero constraints, though this came at the expense of performance.
The assembler automatically calculated relative offsets for Mode 1 instructions, defaulting to this mode if no specific mode was indicated for .NREL addresses, provided that the offset fit within eight bits.
Primary load and store commands included:
- — to load data from memory into an accumulator.
- — to store accumulator data back into memory.
Both instructions supported an "indirect" flag (assembly ), which treated the specified address as a pointer directing to another memory location.
Control transfer instructions consisted of:
- — jump to a given memory address.
- ("jump subroutine") — performs a jump similar to JMP but saves the return address in accumulator 3.
These also allowed indirect addressing with an extra indirection cycle triggered if the highest bit of the indirect address was set. Earlier Nova models prior to Nova 3 imposed no restrictions on how many indirection cycles could occur, potentially causing infinite loops that necessitated system resets.
Memory test operations included:
- — increments a memory word and skips the subsequent instruction if the result is zero.
- — decrements a memory word and skips the following instruction if zero.
These instructions also supported single-level indirect addressing. On Nova systems equipped with magnetic core memory, these tests were executed directly on the memory board using its write-back circuit’s miniature arithmetic unit. This design allowed loop counters to function without occupying accumulators, although these operations ran slower than equivalent arithmetic instructions executed by the CPU.
Examples:
Loads the contents at label into accumulator 1. If resides in .NREL space, this corresponds to:
where '.' denotes the location of the LDA instruction.
Performs an indirect jump through page zero location 17 while saving the return address in accumulator 3. This was typical for RDOS system calls on early Nova models; assembly mnemonic mapped here.
Jumps to the address stored in accumulator 3—commonly used for returning from subroutines since JSR saves return addresses there.
Stores accumulator 0’s value at one address less than that held in accumulator 3.
Decrements the value at , skipping the next instruction if it reaches zero; functionally equivalent to:
assuming lies within .NREL space.
I/O instructions
The Novas employed a channel-based approach for communication with I/O devices, each device featuring two status indicators—"Busy" and "Done"—alongside three registers named A, B, and C. Instructions for I/O could access these registers for reading or writing and issue one of three control signals: "start," "clear," and "pulse." The start signal began an I/O task configured through the A, B, and C registers; the clear signal terminated the operation and reset any interrupts; while the pulse signal initiated auxiliary actions such as disk seek commands. For polled devices, data transfer occurred directly via the A register. In contrast, DMA devices used register A to hold the memory address, B to specify the word count, and C for control flags. Channel 63 was reserved for CPU-specific functions.
Each I/O instruction contained a six-bit channel identifier, a four-bit register selector, and a two-bit field specifying the signal. Assembly language opcodes denoted these signals with suffixes: 'S' for start, 'C' for clear, 'P' for pulse, or no suffix when no signal was sent. Principal opcodes included:
- — move from device A register to accumulator
- — transfer accumulator to device A register
- — move from device B register to accumulator
- — transfer accumulator to device B register
- — move from device C register to accumulator
- — transfer accumulator to device C register
- — send a signal without any register data transfer
Four instructions were dedicated to checking device status:
- — skip next instruction if busy flag is set
- — skip next instruction if busy flag is clear
- — skip next instruction if done flag is set
- — skip next instruction if done flag is clear
Activating a device set its busy indicator; when the operation finished, the busy flag was cleared and the done flag set, frequently causing an interrupt.
Special instructions
These CPU control operations were implemented as shorthand I/O commands on channel 63:
- — acknowledge interrupt; loads the interrupting device’s channel number into the accumulator
- — disable all interrupts globally
- — enable all interrupts globally
- — reset all I/O activities; halts I/O, disables interrupts, and clears pending interrupt signals
- — load interrupt mask from accumulator (device-dependent behavior)
- — read front panel switch settings into accumulator
- — halt CPU execution until manually resumed
Interrupts and interrupt handling
The interrupt system was straightforward but less versatile compared to contemporary CPUs. All interrupt-capable devices shared a single interrupt request line on the backplane. When a device needed attention, it asserted this line; the CPU acknowledged it after completing the current instruction cycle. Devices signaled an interrupt by setting their "done" flag and cleared it once the CPU issued an I/O clear command targeting their channel.
The operating system was expected to place the address of the interrupt service routine at memory location 1. Upon receiving an interrupt, the CPU performed an indirect jump via address 1 after saving the return address in memory location 0 and disabling further interrupts. The interrupt handler then executed an instruction that generated an "acknowledge" signal propagated across devices in sequence on the backplane. The first device that blocked this acknowledge line responded by placing its channel number on the bus, prioritizing devices physically nearer to the CPU.
Using this returned channel number, the OS performed an indexed jump to invoke that specific device’s handler routine. Certain devices—such as the CPU’s power-failure detector—did not respond to this acknowledge instruction; if zero was returned instead, these devices were polled using alternative instructions.
After completing service of the interrupting device, the handler sent an I/O clear command to reset it, re-enabled interrupts with a dedicated instruction that delayed activation by one cycle (to avoid immediate re-interruption), and returned using an indirect jump through memory location 0. This intentional delay prevented interrupts from occurring during the return sequence.
Interrupt priority management was governed by a 16-bit mask loaded via a specific instruction and distributed to all devices. Each device interpreted this mask individually; those masked were expected not to generate interrupts, although enforcement was inconsistent. Some devices disregarded masking altogether.
Systems equipped with magnetic core memory supported recovery from power failures. A dedicated CPU power-failure detection circuit triggered an interrupt upon main power loss, providing time to halt ongoing I/O operations using a specific instruction and save processor registers to memory before power failure completion. Upon power restoration, if the front panel key switch was set to LOCKed position, the CPU performed an indirect jump through memory address 2 to invoke an OS routine responsible for restoring registers and resuming processing—including recovery of interrupted I/O tasks.
Front panel configuration
The majority of Nova units incorporated a front panel console designed for managing and observing CPU operations. Before the introduction of the Nova 3, these consoles followed a uniform design, exemplified by the Nova 840 image. This design featured a keyed power switch, two horizontal rows of lamps indicating address and data, a single row of data entry switches, and function switches that triggered various CPU commands. The address indicator lamps represented the program counter in binary form, while the data lamps displayed values contingent on the current CPU function. An extra lamp signified the carry flag. Most of these lamps were incandescent bulbs, necessitating frequent replacements by Data General’s field technicians.
The data switches allowed manipulation of individual bits within a 16-bit word (numbered 0 through 15 from left to right), serving as inputs for CPU operations or accessible by software through the READS instruction. Function switches operated as two-position momentary toggles: lifting the switch activated the function labeled above it, pressing it triggered the function below, and releasing returned it to a neutral state.
From left to right, the initial four switches controlled EXAMINE and DEPOSIT functions for each of the four accumulators—EXAMINE displayed an accumulator’s contents on the data lamps; DEPOSIT transferred the current data switch settings into that accumulator.
Following these was the RESET/STOP switch: STOP paused CPU operation after completing the ongoing instruction; RESET halted execution immediately, cleared internal registers, and issued an I/O reset signal to peripheral devices. Next to it was the START/CONTINUE switch: CONTINUE resumed program execution at the current program counter location; START loaded bits 1 through 15 from the data switches into the program counter and began processing.
Two additional switches managed memory access: EXAMINE loaded data switch values into the program counter, fetched memory content from that address, and presented it on the display; EXAMINE NEXT incremented the program counter before performing memory examination. DEPOSIT wrote data switch contents into memory at the program counter address; DEPOSIT NEXT incremented before writing.
INST STEP executed a single instruction before halting, facilitating step-by-step debugging. MEMORY STEP performed one clock cycle and then halted—primarily utilized by service technicians for diagnostic purposes.
PROGRAM LOAD initiated system boot by mapping a 32-word boot ROM onto memory start, resetting the program counter to zero, and starting CPU operation. This boot ROM read 256 words (512 bytes) from a designated I/O device into memory and then handed control over to that code. Data switches 8 through 15 selected which boot channel to use; bit 0 indicated whether the device operated in polled or DMA mode. Since the boot ROM did not include device positioning logic, disk drives required manual recalibration to cylinder zero before booting—a procedure often expedited by users through front panel commands.
The power control was a three-position keyed switch: OFF cut all power; ON supplied power but did not automatically start the CPU—users needed to initiate boot via PROGRAM LOAD or equivalent methods. LOCK disabled all front panel function switches and enabled automatic recovery from power failures on systems with core memory; removing the key in either LOCK or OFF positions prevented unauthorized access.
Performance
The Nova 1200 completed core memory access instructions such as LDA and STA in approximately 2.55 microseconds (μs), with read-only memory operations shaving off about 0.4 μs. Instructions involving accumulators (ADD, SUB, COM, NEG, etc.) required around 1.55 μs; multiplication (MUL) took 2.55 μs; division (DIV) lasted about 3.75 μs; ISZ ranged between 3.15 and 4.5 μs. Later models like the Eclipse MV/6000 significantly boosted performance: LDA and STA executed in 0.44 μs, ADD in 0.33 μs, MUL in 2.2 μs, DIV in 3.19 μs, ISZ in 1.32 μs, floating-point addition (FAD) took 5.17 μs, and floating-point multiply/divide (FMMD) required 11.66 μs.
Hello world example
A straightforward Nova assembly program designed for execution on RDOS outputs the phrase “Hello, world.” to the console by utilizing the PCHAR system call: <syntaxhighlight lang="nasm">
; "hello, world" example for Nova on RDOS .titl hello .nrel .ent start
start: dochar: lda 0,@pmsg ; fetch next character mov# 0,0,snr ; skip if zero (string terminator) jmp done .systm .pchar ; print first byte jmp er ; check for error movs 0,0 ; swap bytes .systm .pchar ; print second byte jmp er ; check for error isz pmsg ; advance pointer jmp dochar
done: .systm ; normal program exit .rtn er: .systm ; error exit routine .ertn halt
pmsg: .+1 ; pointer to string start .txt /Hello, world.<15><12>/ 0 ; string terminator
.end start
</syntaxhighlight>
16-bit multiplication routine
To keep costs low, entry-level Nova models were not equipped with dedicated hardware multiply/divide units. The following software subroutine multiplies two 16-bit operands and yields a 16-bit product (overflow is disregarded). It employs a combination of ALU instructions, bit shifts, and conditional skips. When invoked with jsr, AC3 contains the return address, which is utilized by jmp 0,3. Clearing an accumulator is done using sub 0,0, and constants such as -2 or +1 can be loaded in one instruction.
<syntaxhighlight lang="nasm">
mpy: ; multiply AC0 = AC1 * AC2
sub 0,0 ; initialize result to zero mbit: movzr 1,1,szc ; shift multiplier right and test LSB add 2,0 ; add multiplicand if bit set movzl 2,2,szr ; shift multiplicand left and test zero flag jmp mbit ; continue loop if not zero jmp 0,3 ; return from subroutine
</syntaxhighlight>
Binary output of accumulator
This routine outputs the contents of AC1 as a 16-bit binary number on the RDOS console, demonstrating some unique aspects of the Nova instruction set. Notably absent is an instruction to load arbitrary immediate values directly into accumulators; instead, accumulators must be initialized from predefined memory locations (e.g., n16). While architectures such as the PDP-11 and most modern CPUs allow immediate loads, others like the ARM restrict the range of immediate values.
Because the RDOS .systm macro employs jsr, AC3 is overwritten with the return address during the .pchar call. Therefore, this routine saves the caller’s return address in a temporary variable. For recursive or re-entrant code segments, either hardware or software stacks are required. The return instruction jmp @ retrn uses Nova's indirect addressing mode to load the saved program counter.
The constant definitions demonstrate two assembler features: default octal numbering (where 20 equals sixteen) and character constants represented by "0.
<syntaxhighlight lang="nasm">
pbin: ; output AC1 as 16 binary digits on console, by Toby Thain
sta 3,retrn ; save return address
lda 2,n16 ; initialize bit counter to sixteen
loop: lda 0,chr0 ; load ASCII '0'
movzl 1,1,szc ; extract next bit into carry flag
inc 0,0 ; increment to ASCII '1' if bit set
.systm
.pchar ; print character (AC0-2 preserved)
jmp err ; branch if error detected
inc 2,2,szr ; decrement counter and check zero flag
jmp loop ; continue loop if not zero
lda 0,spc ; load space character for output
.systm
.pchar ; print space character
jmp err ; branch if error detected
jmp @retrn ; return using indirect addressing
spc: " ; space character constant chr0: "0 ; ASCII '0' constant n16: -20 ; octal sixteen (-20 octal) retrn: 0 ; storage for return address
</syntaxhighlight>
Applications
The Nova 1200 was utilized by the Canadian Broadcasting Corporation in Montreal for channel play-out automation until the late 1980s. Subsequently, it was succeeded by refurbished Nova 4 models, which continued to operate into the mid-1990s.
See also
- Fairchild 9440 – a single-chip version of the Nova 2 and 3
- National Semiconductor IMP-16 – a 5-chip PMOS processor influenced by the original Nova design
- National Semiconductor PACE and INS8900 – single-chip variants of the IMP-16 featuring byte-level processing capabilities
Bibliography
External links
- Bob Supnik's SimH project – Provides a basic Nova emulator within a flexible framework
- The Portable C compiler (pcc) offers a NOVA target complete with original source code; an alternative repository contains an updated implementation
- Novas Are Forever (SimuLogic) – Hosts extensive DG archives along with both free and commercial offerings
- Portable PDP-8 and DG Nova cross-assembler
- Carl Friend's Minicomputer Museum – Comprehensive documentation of the Nova instruction set