IBM z10

IBM z10
Company type	Microprocessor
Industry	Computer hardware
Founded	February 2008; 18 years ago
Products	Microprocessor for System z10 mainframe

The z10 is a microprocessor created by IBM specifically for the System z10 mainframe computer series, which debuted in February 2008. During its development phase, it was referred to as "z6" and represented a major leap forward in mainframe processing capabilities.

Description

The z10 utilizes the CISC z/Architecture, incorporating four individual cores. Each core is equipped with a 64 KB L1 instruction cache, a 128 KB L1 data cache, and a 3 MB L2 cache—designated as L1.5 by IBM. The processor also features a unified 24 MB L3 cache, which IBM labels as L2.

With dimensions of 21.7×20.0 mm, this chip integrates 993 million transistors manufactured using IBM’s 65 nm SOI CMOS technology (CMOS 11S). It operates at frequencies starting from 4.4 GHz, more than doubling the clock speeds of earlier mainframes such as the System z9, and achieves a 15 FO4 cycle time.

Its connectivity options include two SMP hub ports capable of 48 GB/s each, four memory ports at 13 GB/s apiece, two I/O ports running at 17 GB/s, and a total of 8,765 contacts.

Developed concurrently with the POWER6 processor, the z10 shares several technological aspects such as fabrication methods, logical architecture, execution units, floating-point units, GX bus technology, and a high-speed, low-latency 14-stage in-order pipeline. Nevertheless, it differs considerably in terms of cache hierarchy, SMP topology and protocols, chip layout, and instruction set architecture (ISA). The z10 supports 894 distinct instructions with approximately 75% implemented directly in hardware. Its z/Architecture ensures backward compatibility with the IBM System/360 platform.

Compared to its predecessor—the z9 EC processor—the z10 introduces:

More than fifty new instructions to enhance code efficiency
Optimizations for both software and hardware caches
Capability for handling 1 MB page frames
Hardware-based decimal floating-point operations

The design incorporates comprehensive error detection and correction mechanisms. This includes ECC protection on L2 and L3 caches and buffers, extensive parity verification throughout the chip totaling over 20,000 error detection circuits, and buffered processor states that facilitate precise core retries for most hardware faults.

Storage Control

While the z10 processor itself supports on-chip symmetric multiprocessing (SMP), it relies on an auxiliary companion chip known as the SMP Hub Chip or Storage Control (SC). This companion chip adds an additional 24 MB of off-chip L3 cache and manages communication between z10 processors and Hub Chips at speeds of up to 48 GB/s. The Hub Chip contains 1.6 billion transistors within a die measuring 20.8×21.4 mm and connects via 7,984 interconnects. Each processor can share cache resources across two Hub Chips, allowing for up to 48 MB of shared L3 cache.

Multi-chip module

Within the System z10 Enterprise Class (EC), both z10 processors and Storage Control chips are assembled onto multi-chip modules (MCMs). Each system can accommodate up to four MCMs; one MCM consists of five z10 processors combined with two SC chips—totaling seven chips per module. Due to redundancy considerations and manufacturing variations, not all cores are accessible to customers. The E12, E26, E40, and E56 models each have MCMs providing seventeen active cores per module (with one to four MCMs respectively), whereas the E64 model includes one MCM with seventeen cores alongside three MCMs containing twenty cores each.

External links

Description

Storage Control

Multi-chip module

See also

External links