POWER6
| Industry | Computer hardware |
|---|---|
| Founded | June 16, 1911 in Endicott, New York, United States |
| Headquarters | Armonk, New York , United States |
| Products | POWER6 microprocessor, Power Systems servers, Blade servers, Disk storage systems |
The POWER6 is a microprocessor created by IBM that implements the Power ISA version 2.05. Launched in 2007, it replaced the POWER5+ as IBM's leading Power microprocessor. This chip is part of IBM's eCLipz initiative, which aims to unify the server hardware across the iSeries, pSeries, and zSeries product lines.
History
The POWER6 made its debut at the International Solid-State Circuits Conference (ISSCC) in February 2006, with additional information shared at the Microprocessor Forum in October 2006 and again at ISSCC 2007. Officially unveiled on May 21, 2007, it became available on June 8, 2007, initially running at clock speeds of 3.5, 4.2, and 4.7 GHz. Prototype units reportedly achieved speeds up to 6 GHz. The first silicon samples were manufactured in mid-2005, and by May 2008, the processor was upgraded to operate at 5.0 GHz with the introduction of the P595 system.
Description
The POWER6 features a dual-core design, with each core capable of supporting two-way simultaneous multithreading (SMT). It comprises roughly 790 million transistors on a die measuring 341 mm2, produced using a 65 nm fabrication process. In contrast to the POWER5, the POWER6 executes instructions in-order, which often necessitates recompilation of software for peak efficiency; nonetheless, it still achieves substantial performance improvements over the POWER5+ when running unmodified code.
This processor incorporates IBM's ViVA-2 (Virtual Vector Architecture), enabling the combination of multiple nodes into a single vector processing unit to boost computational throughput.
Each core contains two integer execution units, two binary floating-point units, an AltiVec unit, and an innovative decimal floating-point unit—the first in silicon to provide hardware support for IEEE 754 decimal arithmetic. More than 50 new instructions facilitate decimal calculations and conversions between binary and decimal formats; this capability is also present in IBM's z10 microprocessor.
Regarding cache hierarchy, each core includes a 64 KB four-way set-associative instruction cache alongside a 64 KB eight-way set-associative data cache. Both cores share access to a semi-private unified L2 cache of 4 MiB per core, while an off-chip L3 cache of 32 MiB is shared between the two cores via an interconnect offering an 80 GB/s bandwidth.
The POWER6 architecture supports connectivity with up to 31 other processors through two inter-node links operating at 50 GB/s each and allows up to ten logical partitions per core (totaling 254 per system). A dedicated service processor interface oversees performance tuning and power management according to configurable settings.
The processor employs a clock distribution network operating at a duty cycle correction frequency of 5 GHz using copper wiring and utilizes dual voltage supplies: logic voltage ranges from 0.8 to 1.2 V, while SRAM voltage is approximately 150 mV higher.
Thermal characteristics are comparable to those of the POWER5 generation. IBM addresses power leakage challenges associated with high frequencies by combining manufacturing processes from both 90 nm and 65 nm technologies, as explained by IBM chief scientist Dr. Frank Soltis.
POWER6+
The improved POWER6+ variant was launched in April 2009 and has been incorporated into Power 560 and Power 570 systems since October 2008. This version introduced additional memory keys designed to enhance secure memory partitioning—a capability inherited from IBM's mainframe technology.
Products
By 2008, the POWER6 lineup included "Express" variants (520, 550, 560) aimed at small to medium enterprises, alongside Enterprise class models (570, 595) tailored for extensive data center environments. The Enterprise series features Capacity Upgrade on Demand (CUoD) capabilities and supports hot-swappable processor and memory modules known as "books."
| Model | Socket Count | Core Count | Processor Speed |
|---|---|---|---|
| 520 Express | 2 | 4 | 4.2 or 4.7 GHz |
| 550 Express | 4 | 8 | 4.2 or 5.0 GHz |
| 560 Express | 8 | 16 | 3.6 GHz |
| 570 | 8 | 16 | 4.4 or 5.0 GHz |
| 570 | 16 | 32 | 4.2 GHz |
| 575 | 16 | 32 | 4.7 GHz |
| 595 | 32 | 64 | 4.2 or 5.0 GHz |
IBM also provides a range of four POWER6-based blade servers compatible with AIX, IBM i, and Linux platforms.
| Model | Core Count | Processor Speed | Number of Blade Slots |
|---|---|---|---|
| BladeCenter JS12 | 2 | 3.8 GHz | 1 |
| BladeCenter JS22 | 4 | 4.0 GHz | 1 |
| BladeCenter JS23 | 4 | 4.2 GHz | 1 |
| BladeCenter JS43 | 8 | 4.2 GHz | 2 |
The BladeCenter S and H chassis support blades running AIX, IBM i, and Linux operating systems, whereas the E, HT, and T chassis are compatible with AIX and Linux but do not support IBM i.
At the SC07 event, IBM introduced a water-cooled Power 575 system featuring nodes equipped with up to thirty-two POWER6 cores clocked at 4.7 GHz and memory capacity reaching up to 256 GB RAM; a single chassis can accommodate as many as four hundred forty-eight cores.
| Model | Core Count | Processor Speed | Controller Quantity |
|---|---|---|---|
| DS8700 | 2 or 4 | 4.7 GHz | 1 or 2 |
| DS8800 | 2,4 or 8 | 5.0 GHz | 1 or 2 |
See also
- IBM Power microprocessors
- POWER7
- z10, a mainframe CPU sharing architectural elements with POWER6.
Further reading
- POWER Roadmap, IBM, Oct 2006
- "POWER: The Sixth Generation". (30 October 2006). Microprocessor Report.