OpenPIC and MPIC
| Industry | Computer hardware |
|---|---|
| Products | Multiprocessor Interrupt Controller (MPIC) |
In the early months of 1995, to rival Intel's Advanced Programmable Interrupt Controller (APIC), which facilitated the initial Intel 486-based multiprocessor configurations, both AMD and Cyrix introduced the OpenPIC design capable of handling up to 32 CPUs. Although IBM and Compaq officially endorsed OpenPIC, it never appeared on any x86 motherboard. After OpenPIC did not gain traction in the x86 arena, AMD opted to license the Intel APIC Architecture for its AMD Athlon series and subsequent processors.
The Multiprocessor Interrupt Controller (MPIC), created by IBM, was derived from the OpenPIC register specification. IBM's architecture connects processors to the MPIC via a DCR bus, regulated by a DCR Arbiter. This MPIC supports up to four CPUs and manages 128 interrupt lines. It found use in various PowerPC reference platforms and certain commercial computer models.
IBM implemented an MPIC based on OpenPIC 1.0 within their RS/6000 F50 system and an updated version based on OpenPIC 1.2 in the RS/6000 S70; both systems also incorporated dual 8259 controllers integrated into their PCI-ISA bridge components. Additionally, the RS/6000 7046 Model B50 employed an MPIC.
During the classic Mac OS period, the Apple Hydra's Mac I/O (MIO) chip featured an MPIC alongside controllers for SCSI, ADB, and GeoPort. Apple's initial "Open PIC" implementation in their first MIO chip for the Common Hardware Reference Platform adhered to version 1.2 of the standard, supporting dual processors and up to 20 interrupt sources. Furthermore, an MPIC was embedded within the K2 I/O controller utilized in the Power Mac G5.
Freescale integrates an MPIC compatible with Open PIC across its entire lineup of PowerQUICC and QorIQ processors. The Linux Kernel-based Virtual Machine (KVM) includes support for a virtualized MPIC modeled after Freescale's designs, capable of handling as many as 256 interrupts.