Power ISA
| Company type | Instruction set architecture |
|---|---|
| Industry | Computer architecture |
| Founded | 2006 |
| Founder | IBM, Freescale Semiconductor |
| Parent | OpenPOWER Foundation |
Power ISA represents a reduced instruction set computer (RISC) instruction set architecture developed under the guidance of the OpenPOWER Foundation, with IBM playing a leading role. Initially designed by IBM alongside the now-defunct Power.org, this ISA originated from the PowerPC architecture by integrating the fundamental PowerPC ISA with the optional Book E extension for embedded systems in 2006, a development jointly driven by IBM and Freescale Semiconductor.
Prior to version 3.0, the ISA was segmented into various categories, selectively implemented depending on the processor type; for instance, server-grade processors typically encompass Base, Server, Floating-Point, and 64-Bit sections, with all processors incorporating the Base category.
The Power ISA employs a RISC load/store design featuring several register sets:
- 32 general-purpose registers (GPRs), each 32- or 64-bit wide, dedicated to integer computations.
- 64 vector-scalar registers (VSRs) of 128 bits supporting both vector and floating-point tasks.
- These VSRs include 32 floating-point registers (FPRs) at 64 bits and 32 vector registers (VRs) at 128 bits.
- 8 condition register (CR) fields of 4 bits each, utilized for comparison operations and control flow decisions.
- 11 special-purpose registers such as the Counter Register (CTR), Link Register (LR), time base registers, accumulator (ACC), along with status registers like XER, FPSCR, VSCR, and SPEFSCR.
Instruction lengths up through version 3.0 are predominantly fixed at 32 bits, except for the Variable Length Encoding (VLE) subset tailored to enhance code density in embedded environments. Version 3.1 introduced instruction prefixing to extend support for 64-bit instructions. The architecture accommodates triadic instructions featuring two source operands and one destination operand, supports IEEE 754-compliant single- and double-precision floating-point operations, fused multiply–add (FMA), decimal floating-point instructions, and SIMD instructions processing up to sixteen data elements concurrently.
Power ISA supports both Harvard architecture with separate instruction and data caches and unified cache configurations. Memory access strictly follows load/store semantics but permits out-of-order execution. It offers flexibility in endianness by supporting both big-endian and little-endian addressing modes with per-page endianness control, alongside support for 32-bit and 64-bit address spaces.
The architecture defines operational privilege levels including user mode, supervisor mode, and hypervisor mode.
Categories
- Base – Fundamental components from Book I and Book II
- Server – Book III-S
- Embedded – Book III-E
- Miscellaneous – encompasses floating point, vector processing, signal processing, cache locking mechanisms, decimal floating point, among others.
Books
The Power ISA specification is divided into five distinct parts ("books"):
- Book I – User Instruction Set Architecture: specifies the core instruction set available to application developers, covering memory access, flow control, integer arithmetic, floating-point operations, numeric acceleration units such as digital signal processors (DSPs), and AltiVec extensions.
- Book II – Virtual Environment Architecture: outlines the storage model including aspects like timing constraints, synchronization methods, cache management policies, storage characteristics, and byte ordering rules.
- Book III – Operating Environment Architecture: addresses exception handling, interrupt mechanisms, memory management functions, debugging support, and control features; subdivided into:
- Book III-S – supervisor-level instructions tailored for general-purpose and server-class processors (derived from former PowerPC ISA Book III).
- Book III-E – supervisor-level instructions designed for embedded systems (originating from former PowerPC Book E).
- Book VLE – Variable Length Encoded Instruction Architecture: presents alternative instruction formats drawn from Books I–III aimed at improving instruction density for very low-end applications using 16-bit instructions with big-endian byte ordering.
Compliance
Beginning with Power ISA version 3, full adherence to the entire specification is no longer mandatory for compliance. To address the ISA's complexity, the OpenPOWER Foundation established a tiered compliance framework.
Designs that are compliant must implement the Base architecture along with at least one designated subset:
- SFS – Scalar Fixed-point Subset (129 instructions): covers fundamental fixed-point and load/store instructions, essentially representing the Base.
- SFFS – Scalar Fixed-point + Floating-point Subset (214 instructions): incorporates floating-point instruction support.
- LCS – Linux Compliancy Subset (962 instructions): intended for server-class Linux environments, includes 64-bit support, optional SIMD/VSX, Radix MMU, little-endian mode, and hypervisor capabilities.
- ACS – AIX Compliancy Subset (1099 instructions): designed for AIX compatibility, featuring decimal and quad-precision floating point, big-endian mode, and symmetric multiprocessing.
Additional optional capabilities from LCS, ACS, or Always Optional categories—such as matrix computations and power management—may be implemented but must be fully functional. Custom extensions are permitted within the Architecture Sandbox. When extensions have broader applicability, developers are encouraged to propose them as Requests for Comments (RFCs) to the OpenPOWER ISA Workgroup, with no requirement for OpenPOWER Foundation membership to submit RFCs.
To benefit from the OpenPOWER Foundation’s intellectual property protections under its End User License Agreement (EULA), compliance at a declared subset level is mandatory. Implementations may utilize hardware or firmware mechanisms to fulfill requirements.
EABI and Linux Compliance Divergence
The EABI standards were established before the introduction of the Compliance subsets.
Concerning the Linux Compliance subset’s treatment of VSX (SIMD) as optional: in 2003–2004, 64-bit EABI version 1.9 designated SIMD as optional; however, by July 2015, SIMD became compulsory in EABI version 2.0 to enhance IBM POWER9 system performance. This inconsistency—where SIMD is optional in Linux Compliance but mandatory in EABI v2.0—cannot be easily reconciled without significant disruption, as maintaining backward compatibility with existing Linux distributions is critical. As a result, new OpenPOWER implementations targeting standard Linux distributions are required to support a substantial instruction set of 962 instructions, compared to only 165 instructions mandated by RISC-V RV64GC for Linux operation.
Power ISA v.2.03
Power ISA version 2.03 derives from the earlier PowerPC ISA v.2.02 utilized in POWER5 and later models, alongside the Book E extension of the PowerPC standard. Book I introduced sections addressing auxiliary processing units such as DSPs and the AltiVec vector processing extension.
- Compliant cores
Power ISA v.2.04
Completed in June 2007, Power ISA version 2.04 enhances version 2.03 primarily through updates to Book III-S, which addresses virtualization technology, hypervisor functions, logical partitioning, and virtual memory page management.
- Compliant cores
Power ISA v.2.05
Introduced in December 2007, Power ISA version 2.05 builds upon version 2.04 by enhancing both Book I and Book III-S. This update includes support for decimal arithmetic and advances in server hypervisor functionality.
- Compliant cores
- All cores compatible with earlier Power ISA versions
- POWER6
- PowerPC 476
Power ISA v.2.06
Released in February 2009 and subsequently updated in July 2010, Power ISA version 2.06 expands on v.2.05 by incorporating extensions tailored for the POWER7 processor and the e500-mc core. It introduces vector-scalar floating-point instructions (VSX) and strengthens embedded hypervisor and virtualization features applicable to both single-core and multicore designs.
The revision B issued in November 2010 further enhanced virtualization support.
- Compliant cores
Power ISA v.2.07
Debuting in May 2013, Power ISA version 2.07 advances the capabilities of v.2.06 by improving logical partitioning, transactional memory, and expanding performance monitoring tools. It introduces new storage control mechanisms and updates to VMX and VSX vector instruction sets (VSX-2). This release also incorporates cryptographic enhancements such as AES, Galois Counter Mode (GCM), SHA-224/256/384/512 algorithms (SHA-2), and cyclic redundancy check (CRC) functions. The specification was updated to version 2.07 B in April 2015.
- Compliant cores
Power ISA v.3.0
Following the formation of the OpenPOWER Foundation, Power ISA version 3.0 was introduced in November 2015, removing distinctions between server and embedded workloads while preserving backward compatibility. Key additions include VSX-3 instructions, support for 128-bit quad-precision floating-point operations, a hardware random number generator, hardware-assisted garbage collection, and hardware-enforced trusted computing features. The specification underwent revisions to version 3.0 B in March 2017—eliminating hardware-assisted garbage collection—and to version 3.0C in May 2020, which integrated Compliancy Levels originating from version 3.1.
- Compliant cores
- All cores compatible with earlier Power ISA releases
- POWER9
- OpenPOWER Microwatt
- Libre-SOC focuses on Embedded FP compliance solely with Power ISA 3.0
Power ISA v.3.1
Released in May 2020, Power ISA version 3.1 primarily supports features introduced with the Power10 processor and adds optionality within the instruction set architecture. One significant change is the introduction of "prefixed instructions," allowing instruction lengths of eight bytes compared to the previous four-byte format. Enhancements include broader SIMD and VSX capabilities, with VSX and the SVP64 extension enabling hardware-level support for half-precision (16-bit) floating-point operations.
A notable business benefit is the extension of branch immediate fields to 34 bits through the use of 64-bit prefixed instructions.
The specification was further refined to version 3.1B in September 2021 and updated again to version 3.1C by May 2024.
- Compliant cores
- All cores compatible with prior Power ISA versions
- Power10