POWER4
| Company type | Microprocessor |
|---|---|
| Industry | Semiconductor |
| Predecessor | POWER3, RS64 |
| Founded | 2001 |
| Headquarters | United States |
| Products | 64-bit PowerPC and PowerPC AS microprocessor |
The POWER4 is a microprocessor created by IBM that implements the 64-bit PowerPC and PowerPC AS instruction set architectures. Introduced in 2001, it followed the POWER3 and RS64 processors, allowing IBM's RS/6000 and eServer iSeries (AS/400) servers to operate on a single, unified processor platform, thereby promoting product line integration. As IBM's inaugural multicore processor, the POWER4 incorporated two cores on one chip, representing a major advancement in server CPU technology. Its initial clock frequencies ranged between 1.1 and 1.3 GHz, while the upgraded POWER4+ variant achieved speeds up to 1.9 GHz. The PowerPC 970 is derived from the POWER4 design.
Functional layout
The POWER4 integrates a unified L2 cache segmented into three parts, each managed by an independent L2 controller capable of delivering 32 bytes per cycle. These controllers are linked to the data and instruction caches of both cores through the Core Interface Unit (CIU). Instruction serialization and noncacheable storage operations are handled by a dedicated Non-Cacheable (NC) Unit. Although an on-chip L3 cache controller exists, the actual L3 cache memory is located off-chip. I/O communication is facilitated by the GX bus controller, which employs two separate 4-byte wide buses for inbound and outbound data transfers. The Fabric Controller manages communications between L1/L2 controllers and coordinates multi-chip configurations, supporting up to 32-way multiprocessing and multi-chip modules (MCMs). Additional capabilities include Trace-and-Debug for fault analysis, Built-In Self Test (BIST), Performance Monitoring Unit (PMU), and power-on reset functionality, all contributing to enhanced reliability and performance tracking in enterprise settings.
Execution units
The POWER4 utilizes a superscalar architecture with high-frequency speculative out-of-order execution across eight distinct execution units: two floating-point units (FP1 and FP2), two load-store units (LD1 and LD2), two fixed-point units (FX1 and FX2), a branch unit (BR), and a conditional-register unit (CR). These units can collectively complete up to eight operations per clock cycle, excluding BR and CR:
- Each floating-point unit performs one fused multiply–add operation per clock cycle (equivalent to two operations),
- Each load-store unit executes one instruction per clock cycle,
- Each fixed-point unit completes one instruction per clock cycle.
The pipeline stages encompass branch prediction, instruction fetching, decoding and grouping, dispatching and issuing groups, load-store operations including hit scenarios, followed by instruction execution.
Multi-chip configuration
The POWER4 was also available in a multi-chip module (MCM) format that contained four POWER4 dies within a single package. This configuration provided up to 128 MB of shared L3 ECC cache per MCM, significantly enhancing scalability for high-performance computing applications.
Parametrics
| Clock GHz | 1.3 GHz | |
|---|---|---|
| Power | 115 W at 1.5 V @ 1.1 GHz | |
| Transistors | 174 million | |
| Gate Length | 90 nm | |
| Gate Oxide Thickness | 2.3 nm | |
| Metal Layers Pitch | Thickness | |
| M1 | 500 nm | 310 nm |
| M2 | 630 nm | 310 nm |
| M3-M5 | 630 nm | 20 nm |
| M6(MQ) | 1260 nm | 920 nm |
| M7(LM) | 1260 nm | 920 nm |
| Dielectric Thickness | ~4.2 | |
| Vdd | 1.6 V |
POWER4+
Introduced in 2003, the POWER4+ represented an advancement over its predecessor, achieving clock frequencies up to 1.9 GHz. This processor contained 184 million transistors on a 267 mm² silicon die, manufactured with a 0.13 μm SOI CMOS technology incorporating eight layers of copper interconnects, resulting in enhanced capabilities tailored for enterprise-level server environments.
See also
References
- "Power4 Focuses on Memory Bandwidth". (6 October 1999). Microprocessor Report.
- "IBM's Power4 Unveiling Continues". (20 November 2000). Microprocessor Report.
- POWER4 System Microarchitecture - IBM.
- Tendler et al., "POWER4 system microarchitecture," IBM Journal of Research and Development, vol.46, no.1, pp.5–26, 2002.
- Warnock et al., "The circuit and physical design of the POWER4 microprocessor," IBM Journal of Research and Development, vol.46, no.1, pp.27–52, 2002.