RISC Single Chip

IBM
Industry	Computer hardware, Microprocessors
Headquarters	United States
Products	RISC Single Chip (RSC) microprocessor

The RISC Single Chip (RSC) is a microprocessor developed and manufactured by IBM as a single-chip implementation. It represents a simplified, single-chip adaptation of the multi-chip POWER1 CPU, executing the POWER instruction set architecture (ISA). This processor served as the core for entry-level workstations in the IBM RS/6000 lineup, including Models 220 and 230.

Running at clock speeds of 33 and 45 MHz, the RSC integrates three primary execution units: fixed-point, floating-point, and branch processing units. It also incorporates an 8 KB unified cache that stores both instructions and data. Mirroring the design philosophy of the POWER1, the RSC combines memory controller and I/O capabilities on the same chip through a memory interface unit paired with a sequencer. The processor consists of nine key functional components: fixed-point execution unit (FXU), floating-point execution unit (FPU), memory management unit (MMU), memory interface unit (MIU), sequencer, common on-chip processor unit (COP), instruction fetch unit, and instruction queue/dispatch unit.

The fixed-point execution unit is responsible for processing integer operations, generating addresses for load/store instructions, and managing certain branch instructions via a three-stage pipeline comprising decode, execute, and writeback. Some instructions require multiple cycles to complete during execution.

Floating-point operations are handled by the floating-point unit, which does not implement register renaming due to die size limitations. Its multiply-add hardware operates on 32-bit data; consequently, 64-bit floating-point calculations are divided into two separate passes. The floating-point pipeline consists of four stages: decode, multiply, add, and writeback.

The RSC’s cache is an 8 KB unified structure featuring two-way set associativity with a store-through policy and employing a least recently used (LRU) replacement scheme. Cache lines are sized at 64 bytes and subdivided into four 16-byte quadwords, each tracked by an individual valid bit. The cache supports reading up to four words or writing two doublewords per cycle.

Its memory data bus spans 72 bits—64 bits dedicated to data with an additional 8 bits reserved for error correcting code (ECC). The memory interface oversees this bus and performs ECC verification capable of correcting single-bit errors. Unlike the POWER1’s broader bus width and proprietary memory modules, the RSC utilizes a narrower bus compatible with standard industry SIMMs.

Manufactured using IBM’s 0.8 μm CMOS technology with three metal layers, the RSC contains approximately one million transistors within a die measuring 14.9 mm by 15.2 mm (226.48 mm²). The chip is packaged in a ceramic pin grid array module measuring 36 mm by 36 mm, featuring 201 signal pins. It operates on a 3.6-volt power supply and consumes roughly 4 watts when running at 33 MHz.

See also