POWER1

IBM POWER1
Company type	Microprocessor
Industry	Computer hardware
Founded	1990
Headquarters	Armonk, New York, United States
Products	POWER1 CPU

The POWER1 is a multi-chip CPU created and manufactured by IBM, implementing the POWER instruction set architecture. Originally named the RISC System/6000 CPU or RS/6000 CPU, it was later rebranded to match the naming scheme of its successors (POWERn).

History

Launched in 1990 alongside IBM's RS/6000 POWERserver servers and POWERstation workstations, the POWER1 operated at clock speeds of 20, 25, or 30 MHz. It underwent two enhancements: the POWER1+ introduced in 1991, which ran at 25, 33, and 41 MHz, and the POWER1++ released in 1992, reaching frequencies up to 62.5 MHz due to advancements in semiconductor fabrication. The POWER1 was eventually replaced in September 1993 by the POWER2, an architectural refinement of its predecessor.

Variants include the RISC Single Chip (RSC), a streamlined single-chip model designed for entry-level RS/6000 systems, and the RAD6000, a radiation-hardened version of the RSC tailored for aerospace use. The PowerPC 601, a derivative with reduced features aimed at consumer markets, is indirectly descended from this lineage.

The POWER1 represented several firsts: IBM's initial high-performance RISC processor, the introduction of the POWER ISA, and IBM’s first commercially successful RISC design. It introduced advanced concepts such as register renaming and out-of-order execution, techniques previously confined to mainframe processors, which enhanced superscalar CPU throughput.

This architecture served as the basis for extensive families of POWER, PowerPC, and Power ISA processors, resulting in hundreds of implementations over time.

Support for POWER1 (RIOS) and POWER2 (RIOS2) architectures was discontinued in the open source GCC compiler starting with version 4.5.

Microarchitecture

The POWER1 is a 32-bit CPU featuring two-way superscalar execution with three distinct execution units: a fixed-point unit (FXU), a branch processing unit (BPU), and a floating-point unit (FPU). It supports a 32-bit physical address space alongside a 52-bit virtual address space, allowing programs to utilize up to 4 GB of memory for enhanced performance.

As a big-endian architecture, the POWER1 employs a Harvard cache organization with separate instruction and data caches. The instruction cache ("I-cache") measures 8 KB, is two-way set associative with 64-byte cache lines, and resides on the ICU chip. The data cache ("D-cache") size depends on the system configuration: 32 KB for RIOS.9 and 64 KB for RIOS-1 models; it is four-way set associative with 128-byte lines. The D-cache uses a store-back policy to minimize memory write operations and alleviate potential CPU memory access delays.

Although designed as a high-performance processor, the POWER1 does not support multiprocessing natively, restricting performance gains primarily to increased clock speeds—a significant limitation given its complex multi-chip design. IBM mitigated this by clustering multiple POWER1 systems together, effectively achieving multiprocessing-like scalability as demonstrated by the widely adopted IBM RS/6000 SP. This multiprocessing limitation continued through the POWER2 and P2SC processors; genuine multiprocessing capabilities were only introduced with the arrival of the POWER3 in 1998.

Physical description

The POWER1 processor is a multi-chip central processing unit consisting of several specialized components: an instruction-cache unit (ICU), fixed-point unit (FXU), floating-point unit (FPU), multiple data-cache units (DCU), a storage-control unit (SCU), and an input/output unit. IBM developed two distinct variants by altering the number of DCUs: the RIOS-1 model, which incorporates four DCUs and operates at speeds up to 40 MHz, and the RIOS.9 version, featuring two DCUs running at lower clock rates.

These chips are installed on a "CPU planar" printed circuit board utilizing through-hole mounting technology. The PCB comprises eight layers—four dedicated to power and ground distribution and four for signal routing—to support numerous integrated circuits and accommodate wide data buses.

Manufactured with a 1.0 μm CMOS technology process employing three metal interconnect layers, each chip is packaged in ceramic pin grid array (CPGA) modules containing up to 300 pins and dissipates as much as 4 watts of power. The RIOS-1 configuration integrates roughly 6.9 million transistors—2.04 million allocated to logic circuits and 4.86 million to memory cells—with a total die area measuring approximately 1,284 mm² and a combined count of 1,464 signal pins.

Instruction-cache unit (ICU)

The ICU includes the instruction cache ("I-cache") alongside the branch processing unit (BPU), which encompasses the program counter, condition code register, and loop register. It contains approximately 750,000 transistors—200,000 devoted to logic and 550,000 to SRAM memory—on a die roughly 160 mm² in size (12.7 × 12.7 mm).

The branch processing unit is capable of issuing multiple instructions simultaneously to both fixed-point and floating-point execution queues while managing program flow control instructions out-of-order, handling up to four at once. It employs speculative branch prediction using a dedicated prediction bit; if the predicted branch is not taken, results are discarded, effectively eliminating branch penalties during subroutine calls or interrupts.

The condition code register consists of eight fields: the first two are assigned for fixed-point and floating-point operations respectively, the seventh is reserved for vector instructions, while the remaining fields serve miscellaneous functions. The loop register facilitates "decrement and branch on zero" loops without incurring performance penalties, similar to mechanisms found in digital signal processors such as the TMS320C30.

Fixed-point unit (FXU)

The FXU handles decoding and execution of fixed-point instructions as well as floating-point load/store commands. It incorporates POWER1’s fixed-point register file, an arithmetic logic unit (ALU) for general-purpose instructions, a dedicated multiply/divide hardware block, instruction buffers for both fixed- and floating-point streams (with floating-point instructions forwarded to the FPU), and a two-way set-associative data translation lookaside buffer (D-TLB) containing 128 entries for address translation tasks. The FXU consists of around 500,000 transistors evenly split between logic and memory on a die approximately 160 mm² in area.

Floating-point unit (FPU)

The FPU features a pipelined architecture that executes floating-point instructions dispatched by the ICU, supporting both single-precision (32-bit) and double-precision (64-bit) formats. It performs fused multiply-add operations within a single cycle, improving both computational throughput and numerical accuracy by applying rounding only once per operation.

Additionally, the FPU contains the floating-point register file composed of thirty-two 64-bit registers, six rename registers for out-of-order execution support, and two registers specifically dedicated to division operations.

Data-cache unit (DCU)

The POWER1’s data cache totals 64 KB split into four identical DCUs of 16 KB each. Both the cache memory and connecting buses are protected with error-correcting code (ECC). In configurations with two DCUs (RIOS.9), the memory bus width is 64 bits; in those with four DCUs (RIOS-1), it expands to 128 bits. Essential memory reliability features include memory scrubbing routines, ECC protection, and bit steering capabilities. Each DCU comprises approximately 1.125 million transistors—175,000 used for logic circuits and 950,000 for SRAM—fabricated on a die measuring about 130 mm².

Storage-control unit (SCU)

The SCU chip oversees the POWER1 system by coordinating communication among the ICU, FXU, DCU chips, memory modules, and I/O devices. Although memory scrubbing is performed by the DCUs, the SCU is responsible for managing this process. The SCU contains roughly 230,000 logic transistors and occupies a die area of 130 mm².

I/O unit

Comprising an I/O channel controller (IOCC) and two serial link adapters (SLAs), the I/O unit manages system input/output operations. The IOCC controls the Micro Channel interface and facilitates I/O and DMA transactions between system memory and peripheral adapters. Each SLA supports a serial fiber optic connection designed for linking RS/6000 systems, a capability that was not available at initial release. The I/O unit incorporates approximately 500,000 transistors—300,000 dedicated to logic and 200,000 to memory—on a die measuring 160 mm².