PowerPC 600

AIM Alliance
Industry	Semiconductor
Founded	1991
Headquarters	Austin, Texas, United States
Key people	Engineers from IBM and Motorola
Products	PowerPC 600 series microprocessors (601, 603, 604, 620)

The PowerPC 600 series represents the inaugural line of PowerPC chips created. This development took place at the Somerset facility located in Austin, Texas, where engineers from both IBM and Motorola collaborated as part of the AIM alliance. Established in 1992, the Somerset site focused on producing the first PowerPC processor and advancing general-purpose PowerPC CPUs tailored for personal computer applications. The debut model, the PowerPC 601, was introduced in 1993, followed by subsequent releases including the PowerPC 603, PowerPC 604, and the 64-bit capable PowerPC 620.

Nuclear family

CPU	Pipeline stages	Features
PowerPC 601	4	Three execution units, static branch prediction. Supports SMP.
PowerPC 603	4	Five execution units, branch prediction. Lacks SMP.
PowerPC 604	6	Superscalar design with out-of-order execution and six execution units. SMP capable.
PowerPC 620	5	Features out-of-order execution. Supports SMP.

PowerPC 601

The PowerPC 601 was the pioneering microprocessor to implement the fundamental 32-bit PowerPC instruction set architecture. Its design phase began in mid-1991, with prototype versions completed by October 1992. Commercial availability commenced in October 1993 within IBM’s RS/6000 workstations and later appeared in Apple's inaugural Power Macintosh systems on March 14, 1994. This chip represented a sophisticated single-chip realization of the POWER/PowerPC architecture, developed under a compressed timeline to establish PowerPC’s presence and reinforce the AIM alliance.

To adhere to tight project deadlines while incorporating new capabilities—such as improved performance metrics, added instructions, and PowerPC’s initial implementation of symmetric multiprocessing (SMP)—the design process utilized critical technologies alongside effective project management. It was based on IBM’s earlier RISC Single Chip (RSC) processor architecture but integrated most of the new PowerPC instructions that were not part of the original POWER instruction set. Although significant portions of the RSC design were altered or redesigned—particularly to support a unified I/O bus system and SMP/memory coherence—the RSC foundation helped mitigate risks related to chip area allocation and timing optimization.

Importantly, the 601 not only introduced SMP functionality but also served as a transitional platform between POWER processors and future PowerPC designs, facilitating adoption by IBM and third-party software developers. The development-to-prototype interval was condensed to just one year to expedite market launch.

60x bus

To speed up integration of the 88110 bus architecture into the 601 design, Motorola contributed both their 88110 bus specifications and seasoned engineers who aided in implementing and verifying the 60x bus logic. Since Apple’s system architects were already familiar with Motorola's well-documented 88110 I/O bus, this technology was adopted to shorten time to market. After being incorporated into the 601, this interface was renamed the 60x bus. The project involved collaboration among Motorola personnel, several Apple designers, and over 120 IBM engineers.

Basing the bus on the existing 88110 standard streamlined development timelines by minimizing redesign efforts for Apple's support ASIC components and reducing negotiation complexity around processor design interfaces. This approach effectively prevented potential "Bus Wars" that management had aimed to avoid if a new bus had been created from scratch. However, this choice did create challenges for IBM’s initial RS/6000 system design team since their ASICs were constructed around an incompatible RSC bus architecture.

The 60x bus evolved into a durable interface standard supporting multiple PowerPC processors such as the 601, 603, 604, G3, G4, as well as Motorola/Freescale’s PowerQUICC processors.

Design

Developed to serve a wide range of uses, this chip supported external L2 cache and symmetric multiprocessing. It comprised four execution units: a floating-point unit, an integer unit, a branch unit, and a sequencer. The processor incorporated a memory management unit and featured pipelines of different lengths—four stages for integer instructions, two for branches, five for memory operations, and six for floating-point tasks.

Introduced in IBM systems toward the end of 1993, the chip was branded as PPC601 by IBM and MPC601 by Motorola, with clock speeds ranging from 50 to 80 MHz. Manufactured using a 0.6 μm CMOS technology with four aluminum interconnect layers, the die size was 121 mm² housing 2.8 million transistors. Its 32 KB unified L1 cache was exceptionally large for its era, enabling performance that outpaced rival processors such as Intel's Pentium. The PowerPC 601 powered early Power Macintosh systems from Apple, along with various IBM and Groupe Bull RS/6000 workstations and SMP servers.

IBM was the sole manufacturer of both the 601 and its successor, the 601+, producing them at facilities in Burlington, Vermont, and East Fishkill, New York. The original 601 utilized IBM's CMOS-4s process, while the 601+ transitioned to CMOS-5x. Although uncommon, some units were rebranded with Motorola logos for distribution purposes. This is significant given Motorola’s effective marketing that led to the 601 being named one of Time Magazine’s "Products of the Year" in 1994 under their branding.

PowerPC 601 Microprocessor, lecture by Keith Diefendorff

PowerPC 601v

The PowerPC 601v—also known as the PowerPC 601+—was released in 1994, running at frequencies between 90 and 120 MHz. Produced using a 0.5 μm CMOS process with four interconnect layers, its die measured 74 mm². The transition from CMOS-4s to CMOS-5x was managed exclusively by an IBM team using IBM EDA tools and manufacturing sites to prevent delays in time-to-market.

PowerPC 603

Introduced in 1994, the PowerPC 603 was the first processor to fully implement the 32-bit PowerPC Architecture. It offered advanced dual-issue capabilities (extending up to three instructions with branch folding) alongside out-of-order execution, all while maintaining low power consumption at 2.2 W and featuring a compact die size of 85 mm². Targeted at portable devices, it included power-saving features that reduced energy use to just 2 mW during sleep mode. The design incorporated a four-stage pipeline and five execution units, complemented by separate 8 KB L1 instruction and data caches. It supported clock speeds up to 120 MHz at a voltage of 3.8 V but did not provide hardware support for symmetric multiprocessing (SMP).

With a transistor count of approximately 1.6 million, both IBM and Motorola fabricated the 603 using a 0.5 μm CMOS process with four metal interconnect layers. At an operating frequency of 80 MHz, it consumed around 2.2 W. The architecture of this processor directly influenced the later PowerPC 750 ("G3") series.

Apple initially planned to integrate the 603 into portable Macintosh computers but found its relatively small caches insufficient for delivering acceptable performance when running legacy 68K emulation software. As a result, Apple restricted its deployment primarily to affordable Performa desktop models. This limitation postponed releases such as the PowerBook 5300 and Duo 2300 while Apple awaited updated processors. The Performa 5200’s association with the PowerPC 603 contributed to a negative perception due to design issues unrelated to the CPU itself, including network instability and bus faults. Additionally, the processor was retrofitted onto older motherboard designs, which further exacerbated performance difficulties. Despite these challenges, the PowerPC 603 achieved extensive use in embedded system applications.

PowerPC 603e and 603ev

The PowerPC 603e improved upon the original 603 by expanding the L1 cache to 16 KB, organized as a four-way set-associative cache for both data and instructions. Its clock frequency doubled, reaching 200 MHz, while a die shrink to a 350 nm process allowed the PowerPC 603ev variant to operate at speeds up to 300 MHz. Both chips contain approximately 2.6 million transistors, with die dimensions of 98 mm² for the 603e and 78 mm² for the 603ev. The 603ev’s maximum power consumption is around 6 W at its top speed of 300 MHz.

The 603e was the first widely available desktop processor to achieve a clock speed of 300 MHz, powering machines such as the Power Macintosh 6500. It was also integrated into Phase5 accelerator cards for Amiga systems, running between 160 and 240 MHz. This processor continues to be marketed by IBM, Freescale, and other manufacturers including Atmel and Honeywell, the latter producing a radiation-hardened RHPPC version. The multiprocessing BeBox from Be Inc. utilized the 603e despite its core not originally supporting multiprocessing. IBM incorporated it into the IBM ThinkPad 800 series, while LeCroy Corporation employed it in digital oscilloscopes. Moreover, each of the 66 satellites in the Iridium phone constellation uses seven Motorola/Freescale PowerPC 603e processors running near 200 MHz. A specialized variant of the 603e is also implemented in the Mark 54 Lightweight Torpedo.

G2

Freescale renamed the PowerPC 603e core as G2, which serves as the basis for numerous embedded PowerQUICC II processors within the MPC82xx lineup, with clock rates scaling up to 450 MHz. The G2 label is also applied retroactively to align with subsequent generations such as G3, G4, and G5.

e300

Further advancements led Freescale to develop the e300 core from the 603e design, powering PowerQUICC II Pro embedded processors in the MPC83xx series. These feature enlarged L1 caches of 32 KB each for data and instructions alongside other enhancements that boost performance. These system-on-chips can run at frequencies reaching 667 MHz. The e300 core is also employed in the MPC5200B SoC used in compact devices like the EFIKA computer.

PowerPC 604

Introduced in December 1994 alongside the 603, the PowerPC 604 was engineered for high-performance workstations and entry-level servers, incorporating hardware support for symmetric multiprocessing. It found widespread application in Apple’s premium systems, Macintosh clone computers, IBM’s entry-level RS/6000 servers and workstations, accelerator boards for Amiga, as well as telecommunications embedded systems.

As a superscalar design, the 604 was capable of issuing up to four instructions per cycle through a six-stage pipeline supported by six parallel execution units. It could complete as many as six instructions each cycle. The processor contained two simple integer units, one complex integer unit, a dedicated floating-point unit, a branch unit with out-of-order execution, and a load/store unit. Separate L1 caches were provided for data and instructions at sizes of 16 KB each, while a 32- or 64-bit 60x bus operated at speeds up to 50 MHz.

Manufactured by IBM and Motorola using a 0.5 μm CMOS process with four layers of interconnects, this chip integrated approximately 3.6 million transistors on a die measuring 196 mm². Its power consumption ranged from 14 to 17 W at a clock speed of 133 MHz, with operating frequencies spanning from 100 to 180 MHz.

PowerPC 604e

Released in July 1996, the PowerPC 604e delivered approximately a 25% boost in performance by incorporating a condition register unit, distinct 32 KB L1 caches for data and instructions, an enhanced memory subsystem, and branch prediction capabilities. It consisted of 5.1 million transistors and was manufactured by IBM and Motorola utilizing a 0.35 μm CMOS technology with five layers of interconnects. The die sizes measured 148 mm² for Motorola and 96 mm² for IBM, operating between 166 and 233 MHz while consuming 16–18 watts, and supporting memory buses up to 66 MHz.

PowerPC 604ev "Mach5"

The PowerPC 604ev—also referred to as 604r or "Mach 5"—was introduced in August 1997 as an upgraded version of the 604e, produced by IBM and Motorola on a 0.25 μm CMOS fabrication process. It achieved higher clock rates ranging from 250 to 400 MHz with reduced power usage (6 watts at 250 MHz) and accommodated memory buses up to 100 MHz. The die area was compact at 47 mm².

Although Apple discontinued the use of the 604ev in favor of the PowerPC 750 in 1998, IBM continued employing this processor in cost-sensitive entry-level RS/6000 systems for several subsequent years.

PowerPC 620

The PowerPC 620 represented the initial comprehensive implementation of the 64-bit PowerPC architecture, targeting premium workstations and server platforms. Despite being developed concurrently with the 603 and 604 models, its launch was postponed until 1997. Even with its sophisticated design, it underperformed compared to the more economical 604e, which limited its market penetration.

Motorola fabricated the chip using a 0.5 μm process containing 6.9 million transistors on a die size of 311 mm². It operated within a frequency range of 120 to 150 MHz, consuming roughly 30 watts at a clock speed of 133 MHz. A subsequent revision employing a finer 0.35 μm process enabled clock speeds up to 200 MHz.

Sharing architectural similarities with the 604, the 620 featured a five-stage pipeline and supported symmetric multiprocessing. Its execution units included load/store, branch, floating-point unit (FPU), plus three integer units. Cache sizes were improved to include separate instruction and data caches of 32 KB each, with support for L2 caches up to 128 MB. Enhancements also encompassed advanced branch prediction mechanisms and out-of-order execution support. The floating-point unit was upgraded to provide hardware acceleration for essential instructions such as square root operations, complemented by faster data buses for increased throughput.

Despite its capabilities, the PowerPC 620 saw limited production volumes and was primarily utilized by Groupe Bull within Escala UNIX systems. IBM redirected efforts towards more powerful processors like the RS64 and POWER3 series for their server offerings.

6XX, MX, and future buses

The 6XX bus was engineered as a 128-bit system bus tailored for multiprocessor environments, facilitating connections among CPUs, caches, memory modules, and input/output components through a system control chip. It supported both 32-bit and 64-bit PowerPC processors along with memory addressing beyond the traditional 32-bit limit and accommodated NUMA architectures. This bus architecture was employed in POWER3, RS64, and RS/6000 systems based on the 604 processor family using the "Orca" bridge chip.

Serving as the input/output interface in systems built around the 6XX bus was the MX I/O bus. Early chipset designs—named after various snakes—acted as bridges between the 6XX and MX buses while linking MX to conventional I/O buses.

Over time, the original 6XX bus evolved into a distributed coherent interconnect known as the Fabric Bus, whereas the MX bus transitioned into what became known as the GX bus, named after IBM’s GigaProcessor initiative; both were implemented within POWER4 processors. Later enhancements produced iterations labeled GX+ and GX++, which appeared in POWER5 and POWER6, respectively. Additionally, versions of the GX bus are utilized within IBM's high-end mainframe systems including the z10 and z196 System z platforms.

PowerPC 602

The PowerPC 602 was a streamlined variant of the PowerPC 603, jointly developed by Motorola and IBM with a focus on gaming consoles, and introduced in February 1995. It incorporated smaller L1 caches—4 KB for instructions and 4 KB for data—a single-precision floating-point unit, and a simplified branch prediction mechanism. Operating frequencies ranged from 50 to 80 MHz, with power consumption measured at 1.2 W when running at 66 MHz. The processor contained around one million transistors on a 50 mm² die, produced using a 0.5 μm CMOS fabrication process featuring four layers of interconnect.

The 3DO Company designed the M2 console to utilize two PowerPC 602 CPUs; however, this console never reached the commercial market.

PowerPC 603q

On October 21, 1996, the fabless semiconductor firm Quantum Effect Devices (QED) revealed the PowerPC 603q at the Microprocessor Forum. Despite its designation, this processor was a fresh implementation of the 32-bit PowerPC architecture targeting high-performance embedded applications. The 603q combined compact size, low power consumption, and strong performance—rivaling the more costly PowerPC 603e but with greater energy efficiency. It featured an in-order five-stage pipeline with a single integer execution unit, a double-precision floating-point unit adapted from the R4600, and separate caches of 16 KB for instructions and 8 KB for data. Manufactured using a 0.5 μm process technology, it occupied a die area of 69 mm² and drew only 1.2 W at a clock speed of 120 MHz.

Although developed for Motorola, the project was terminated when Motorola withdrew prior to mass production. Without holding a PowerPC license, QED was unable to commercialize the chip, resulting in its cancellation.

PowerPC 613

The PowerPC 613 is thought to be Motorola’s internal label for a third-generation PowerPC processor. It is believed to have been renamed "PowerPC 750" as a response to Exponential Technology’s x704 processor, which was designed to surpass the capabilities of the PowerPC 604. However, documentation is limited and this connection remains speculative or possibly refers to another processor altogether.

PowerPC 614

In a similar vein, the PowerPC 614 is presumed to be another Motorola codename for a third-generation PowerPC that was later rebranded—likely as the "PowerPC 7400". Motorola reportedly considered this model part of their fourth generation despite minimal architectural changes distinguishing it from the "G3" series. As with the PowerPC 613, available information is scarce and may reflect conjecture or confusion with other designs.

PowerPC 615

Introduced by IBM in 1994, the PowerPC 615 was an experimental processor integrating an x86 core on the same die, enabling native execution of both PowerPC and x86 instruction sets. It supported either pure 32-bit or 64-bit PowerPC code, pure x86 (32-bit), or mixed instruction streams with very low overhead when switching contexts. Only Minix and a specialized development version of OS/2 were compatible with this hybrid architecture.

Built on a 0.35 μm process with a die size of approximately 330 mm², it was pin-compatible with Intel’s Pentium processors and offered comparable performance. The project was ultimately discontinued partly due to insufficient backing from Microsoft. Engineers involved later contributed their expertise to Transmeta’s Crusoe CPU development. Meanwhile, improvements in dynamic binary translation software such as Digital’s FX!32 raised questions about the necessity of hardware dedicated to foreign instruction execution versus focusing on optimizing native processing speed.

PowerPC 625

PowerPC 625 served as the initial internal label for IBM's Apache lineup of 64-bit PowerPC CPUs, which utilized the "Amazon" PowerPC-AS instruction set architecture. This designation was never marketed publicly; instead, these processors were ultimately released under the "RS64" brand.

PowerPC 630

The PowerPC 630 was IBM's preliminary title for a premium 64-bit processor aimed at merging the POWER and PowerPC instruction sets. To distinguish it from consumer-focused PowerPC chips used by Apple, it was subsequently renamed "POWER3".

PowerPC 641

The project known as "PowerPC 641", with the codename Habanero, was an IBM PowerPC initiative active between 1994 and 1996 that was ultimately canceled. It is thought to represent the third generation of PowerPC processors, building upon the foundation of the 604 model.

External links

PPC 600 at mackido.com