SDS 9 Series
| Industry | Computer hardware |
|---|---|
| Founded | 1960s |
| Fate | Replaced by SDS Sigma series |
| Products | SDS 9 Series computers (SDS 910, SDS 920, SDS 925, SDS 930, SDS 940, SDS 945, SDS 9300) |
The SDS 9 Series computers represent a family of transistor-based systems developed by Scientific Data Systems during the 1960s and 1970s, designed with backward compatible capabilities. This collection includes models such as the SDS 910, SDS 920, SDS 925, SDS 930, SDS 940, and SDS 945. Additionally, the SDS 9300 expands on the 9xx architecture. In contrast, the 1965 SDS 92 is a distinct, incompatible 12-bit machine constructed with monolithic integrated circuits.
The initial releases were the 910 and 920, which became available starting in August 1962; the SDS 9300 was introduced in June 1963. Subsequent models followed: the 925 and 930 in 1964, the 940 in 1965, and finally the 945 in 1968.
This series was eventually replaced by the SDS Sigma series.
General description
Each system in this lineup is a 24-bit single-address architecture featuring programmer-accessible registers: A (accumulator), B (extension), X (index), and P (a 14-bit program counter), alongside an overflow flag. The SDS 9300 enhances this setup by including three additional index registers (X1 through X3) to facilitate base-plus-offset addressing, enabling access to memory beyond the standard 16K word limit. Input/output operations are managed via W and Y registers.
The maximum addressable memory varies across models: the SDS 910 and 920 accommodate up to 16,384 words (16KW); both the SDS 9300 and SDS 930 support up to 32K words; while the SDS 940 and SDS 945 can handle up to 64K words. Each model employs different mechanisms to manage memory exceeding the initial 16K boundary.
Data formats
Fixed-point numbers are represented using a big-endian two's complement format spanning 24 bits.
Floating-point arithmetic is generally implemented through software routines using programmed operators, except on the SDS 9300 which incorporates hardware support for floating-point operations. Floating-point values occupy double words of 48 bits: single precision uses a signed fraction of 24 bits combined with a signed exponent of 9 bits; double precision employs a fraction of 39 bits alongside a similarly sized exponent. Both components utilize big-endian two's complement encoding. The number format corresponds to F×2^E, where F denotes the fraction and E the exponent.
Floating-point structure details:
Double-precision floating-point
+-+-----------------------+
|±| Fraction | high-order word
+-+-----------+-+---------+
| frac(cont) |±|exponent | low-order word
+-------------+-+---------+
bit positions:
High-order word:
bit 0 fraction sign
bits1–23 high-order fraction
Low-order word:
bits0–14 low-order fraction
bit15 exponent sign
bits16–23 exponent
Single-precision floating-point
+-+-----------------------+
|±| Fraction | high-order word
+-+-----------+-+---------+
| not used |±|exponent | low-order word
+-------------+-+---------+
Identical to double precision but utilizes only a 24-bit fraction.
Address generation
When generating addresses, indexing is applied prior to indirection as specified by indexed absolute addressing. The word located at the effective indirect address is interpreted similarly to an instruction (excluding its opcode), allowing indirect addresses to specify further levels of indexing or additional indirection. This mechanism supports multiple layers of indirect addressing.
Programmed operators
The programmed operator capability leverages the six-bit instruction code to invoke a vector table containing up to sixty-four subroutine addresses (octal range from 00 to 77). When the P bit is active, an instruction code xx triggers execution at location 1xx (octal). The address of the POP instruction is stored at location zero; here, bit zero reflects the current overflow flag status (which is then cleared), and bit nine is set to '1'b indicating an indirect address. This design enables programmed operator routines to access data indirectly via the address provided by the POP instruction.
SDS 910
The SDS 910 is equipped with magnetic-core memory ranging from 2048 to 16384 words, operating with an 8 μs cycle time. Fixed-point addition completes in 16 μs, whereas multiplication requires 248 μs. It comes standard with two hardware interrupts, expandable up to a maximum of 896.
Instruction layout for both the 910 and 920 models:
+-+-+-+------+-+--------------+
|0|X|P|Opcode|I| Address |
+-+-+-+------+-+--------------+
1 2
bit 0 1 2 3 8 9 0 3
Bits 0–2: "tag"
Bit 0: always set to zero.
Bit 1: set to '1' if the operand address uses indexing.
Bit 2: set to '1' when the instruction is a programmed operator (POP).
Bits 3–8: instruction code or programmed-operator identifier.
Bit 9: set to '1' if the operand address is indirected (indexing occurs before indirecting).
Bits10–23: operand address.
The approximate weight of the SDS 910 is around 900 pounds.
SDS 920
The SDS 920 provides magnetic core memory capacities from 4096 up to 16384 words. Its fixed-point addition speed matches the SDS 910 at 16 μs, while multiplication time improves significantly to approximately 128 μs. The system supports up to 1024 priority interrupts.
This model weighs roughly 1000 pounds.
SDS 930
The SDS 930 introduces a memory extension system that allows addressing beyond the initial limit of 16,284 words. It includes two separate three-bit registers, EM2 and EM3, which serve as the high-order three bits in forming the effective address. Addresses within the range of octal 00000 to 17777 (the first 8,192 words) remain unchanged. For instructions whose highest octal digit is two or three, the corresponding EM2 or EM3 register substitutes that digit.
To ensure backward compatibility, EM2 and EM3 are preset at startup to values of two and three respectively, enabling programs to access up to a total of 16,384 words. Both registers are programmable by software.
The program loader takes advantage of an otherwise unused high-order instruction bit as a relocation indicator.
With a memory cycle time reduced to 1.75 μs, fixed-point addition requires only 3.5 μs and multiplication completes in about 7.0 μs. The priority interrupt architecture accommodates between two and thirty-eight I/O interrupts and supports up to eight hundred ninety-six system interrupts.
Instruction format remains consistent with earlier models except for the inclusion of extended memory bits:
+-+-+-+------+-+--+----------+
|0|X|P|Opcode|I|EM| Address |
+-+-+-+------+-+--+----------+
bit 0 1 2 3 3 9 11 1 2
01 2 3
Bits10 and11 indicate whether extended memory is used:
EM='00'b denotes no extension (first8K words),
EM='10'b prepends EM2 contents,
EM='11'b prepends EM3 contents for effective addressing.
SDS 940
The SDS940 introduces multi-user capabilities through distinct operating modes: normal mode, which replicates behavior from previous models; monitor mode, which restricts I/O operations and privileged instructions; and user mode, designed for running application programs.
The system employs eight memory map registers, each corresponding to a block of two thousand words, collectively creating a virtual address space of sixteen thousand words.
In normal mode, instruction format aligns with that of the SDS930. However, user mode addressing diverges by utilizing bits that specify both a virtual memory block number and an offset within that block. The content of the memory map register associated with the block is prepended to form the effective address:
SDS940 user mode instruction format:
+-+-+-+------+-+---+---------+
|U|X|P|Opcode|I|Blk| Address |
+-+-+-+------+-+---+---------+
bit 0 1 2 3 ... ...
... ...
Bit0 is ignored unless bit2 (P) indicates a programmed operator; in that case, '1' signifies a system POP ("SYSPOP").
Bits10–12 identify the virtual memory block number (memory map register),
bits13–23 specify the address within that block.
Memory map
The 940 utilizes a memory map to facilitate virtual memory access, with distinctions between user and monitor modes.
In user mode, the upper three bits of an instruction's address select one of eight registers (R0–R7). Each register stores a 5-bit value (Rn) that is combined with the lower 11 bits of the address to create a 16-bit physical address. This segmentation divides virtual memory into eight blocks of 2048 words each, enabling simultaneous access to 16K words out of a total 32K physical words. A sixth bit (Pn) indicates read-only blocks; when Rn=0 and Pn=1, it signals an unallocated block, triggering a trap. Only in monitor mode can these map registers be modified.
The monitor mode memory map operates similarly but omits the P bits. Registers M0–M5 hold fixed read-only values ranging from 0 to 5, providing direct addressing for physical locations from 0 up to 8K-1. For addresses between 8K and 12K-1, the memory extension register EM2 generates the physical address; addresses from 12K to 16K-1 rely on registers M6 and M7.
The monitor has the capability to toggle between its own memory map and the user's map by using instruction bit 0, which grants access to the user's address space.
System programmed operators
User mode programmed operators interact with user virtual addresses ranging from 100 to 1778. Additionally, the 940 supports System Programmed operators (SYSPOPS), which enable entry into monitor mode and execution of instructions located at the monitor's physical vector addresses 100–1778, thereby invoking monitor services.
SDS 945
The SDS 945 represents an upgraded iteration of the 940 time-sharing system, marketed as supporting up to 24 concurrent users and accommodating as many as 64 authorized users.
MAGPAK
The MAGPAK subsystem, consisting of the 9446 tape drive and SDS 9401 tape cartridge, was created for the SDS 900 series and introduced in May 1964. This system features two magnetic tape drives controlled independently and mounted on a standard panel. Data is recorded at a speed of 7.5 inches per second with a density of 1,400 bits per inch. The drives connect to any Series 900 system through the 9448 Tape Control Unit. Each cartridge contains roughly 600 feet of Mylar tape with two tracks capable of storing around four million six-bit characters per cartridge.
Software
Apart from the 940 and 945 models, the primary operating system for this series is MONARCH, a single-task batch OS. Initially loaded from magnetic tape, later versions operate from a head-per-track magnetic disk known as a RAD (Rapid Access Data) File. MONARCH serves as a monitor, overseeing transitions between jobs and providing application support services; however, it does not function as an executive system, since applications maintain full control over computer resources during execution.
Included among standard system routines embedded within the monitor are:
- The MONARCH Loader
- The MONARCH update routine
- Standard input/output subroutines
- The Meta-Symbol assembler
- FORTRAN II compiler
By 1969, an ALGOL 60 compiler had also become available.