InfiniteReality

InfiniteReality

Company type	Hardware architecture family
Industry	Computer graphics, Visualization
Founded	1996
Founder	Silicon Graphics
Defunct	2005
Products	3D graphics hardware architectures, visualization systems

InfiniteReality represents a family of 3D graphics hardware architectures developed by Silicon Graphics between 1996 and 2005. Serving as Silicon Graphics' premier visualization solution for their MIPS/IRIX environment, InfiniteReality was exclusively integrated into their Onyx visualization platforms, which were frequently referred to as "graphics supercomputers." Its primary audience comprised large corporations and academic organizations specializing in computer simulations, digital media production, engineering, and scientific research.

InfiniteReality

Launched in early 1996 alongside the Silicon Graphics Onyx workstation, InfiniteReality replaced the earlier RealityEngine, which continued to be offered as a cost-effective option for deskside workstation setups.

As a third-generation sort-middle design, InfiniteReality aimed to deliver complex scene rendering at 60 frames per second—achieving speeds two to four times faster than its predecessor, RealityEngine. It was finely tuned for OpenGL and incorporated the majority of the OpenGL rendering pipeline directly in hardware.

The architecture is segmented into three principal circuit boards that correspond to distinct pipeline phases: Geometry (Geometry Engine), Raster Memory (Raster Manager), and Display Generator. This modular arrangement reflected RealityEngine’s structure to simplify system upgrades. Each graphics pipeline consists of one Geometry Engine board, between one and four Raster Manager boards, and one Display Generator board.

The design employs twelve ASIC types fabricated with 0.5 and 0.35-micron semiconductor processes featuring three layers of metal interconnects, powered by a 3.3 V supply. A fully loaded pipeline integrates 251 million transistors and was engineered by a team of 55 specialists.

High-performance Onyx2 and Onyx 3000 configurations could accommodate up to 16 InfiniteReality pipelines functioning in three distinct modes: multi-seat (enabling up to eight users per pipeline with individual displays and input peripherals), multi-display (supporting multiple display outputs for applications such as virtual reality), and multi-pipe. The multi-pipe mode offers two options: employing a digital multiplexer (DPLEX) daughterboard to merge outputs or utilizing MonsterMode software to distribute frame rendering tasks across multiple pipelines.

Communication between pipelines and the host system is facilitated via a Flat Cable Interface (FCI), linking the Host Interface Processor ASIC on the Geometry Board with the Ibus on the IO4 board inside the host machine.

Geometry board

The Geometry board is responsible for processing geometry and image data through four distinct stages, each handled by dedicated components. The initial stage, called the Host Interface, supports two system variants: the traditional shared memory Onyx using the POWERpath-2 bus, and the distributed shared memory Onyx2 leveraging the NUMAlink2 interconnect. To manage bandwidth differences—200 MB/s for POWERpath-2 versus 400 MB/s for NUMAlink2—the InfiniteReality incorporates a Host Interface Processor, an embedded RISC processor that retrieves display list objects via direct memory access (DMA). This processor is paired with 16 MB of SDRAM, of which 15 MB functions as a cache for display leaf objects, delivering data at speeds exceeding 300 MB/s to subsequent stages.

The Geometry Distributor passes data and commands from the Host Interface Processor to individual Geometry Engines. Each Geometry board can contain up to four Geometry Engines operating under a MIMD model. The Geometry Engine itself is a semi-custom ASIC featuring a SIMD pipeline with three floating-point cores; each core includes an arithmetic logic unit (ALU), multiplier, and a register file sized at 32 bits by 32 entries. Additionally, it houses a 32-bit by 2,560-entry memory used for OpenGL state management and scratchpad functions, along with a converter that translates floating-point values into fixed-point integers.

Running at a clock speed of 90 MHz, each Geometry Engine executes three instructions per cycle. With four engines on one board, total throughput reaches 2.16 GFLOPS; scaling this to sixteen pipelines results in a maximum of 34.56 GFLOPS. The engine uses compressed microinstructions of 195 bits to reduce bandwidth requirements and chip area without significantly compromising performance.

The last stage, known as the Geometry-Raster FIFO, consolidates outputs from all four Geometry Engines into a single ordered data stream. This buffer is constructed from SDRAM with a capacity of 4 MB, capable of holding up to 65,536 vertices. The transformed vertex information is then transmitted over the Triangle Bus (also called Vertex Bus), which provides a bandwidth of 400 MB/s to Raster Manager boards responsible for triangle setup and reassembly.

Raster Memory board

The Raster Memory board is responsible for rasterization and houses both the texture memory and the raster memory. Rasterization takes place within the Fragment Generator alongside eighty Image Engines. The Fragment Generator comprises four ASIC components: the Scan Converter (SC), Texel Address Calculator (TA), Texture Memory Controller (TM), and Texture Fragment (TF).

The SC and TA ASICs carry out scan conversion, interpolate color and depth values, perform perspective-correct texture coordinate interpolation, and calculate levels of detail. Their output is directed to eight TM ASICs, which are specialized controllers managing texel access in memory. Each TM ASIC governs four 16-bit wide SDRAM modules, representing one-eighth of the texture memory capacity. Raster Manager boards utilize 4 Mb SDRAM chips for a total of 16 MB texture memory or 16 Mb SDRAM chips to reach 64 MB texture memory. TM ASICs conduct texel retrievals and send the texels onward to TF ASICs, where texture filtering, environment combining, and fog effects are applied. To link 32 SDRAM units with 80 Image Engines efficiently, TM and TF ASICs employ a two-rank omega network, streamlining interconnect pathways.

Each of the eighty Image Engines controls a segment of raster memory—1 MB SGRAM arranged as 262,144 by 32-bit words in InfiniteReality—and performs OpenGL fragment-level operations such as pixel ownership testing, stencil testing, depth buffering, blending, dithering, and logical operations. They also manage anti-aliasing and accumulation buffer capabilities. Pixel data from Image Engines is transmitted through a 2-bit serial bus to the Display Generator board; bandwidth distribution varies based on the number of Raster Manager boards installed. The Video Bus offers a bandwidth of 1.2 GB/s. Four Image Engine cores are integrated into a single ASIC containing approximately 488,000 logic gates and 1.95 million transistors on a 42 mm² die manufactured using a 0.35-micron process by VLSI Technology.

InfiniteReality employs either RM6-16 or RM6-64 Raster Managers. Each pipeline can support display resolutions of 2.62 million, 5.24 million, or 10.48 million pixels when equipped with one, two, or four Raster Manager boards respectively. Configurations for raster memory allow for pixel depths of 256, 512, or 1024 bits per pixel; for instance, a 320 MB setup accommodates a resolution of 2560×2048 at 512 bits per pixel. When utilizing four Raster Managers, texture memory bandwidth reaches up to 15.36 GB/s while raster memory bandwidth attains 72.8 GB/s.

Display Generator board

The DG4-2 Display Generator board supports up to two video outputs by default and can be expanded to eight outputs through an optional daughterboard known as the DG4-8. Each output channel includes dedicated hardware for video timing control, image resizing, gamma correction, genlock, and an 8-bit digital-to-analog converter capable of handling pixel clocks up to 220 MHz.

Video streams are managed by four ASICs that de-serialize and de-interleave incoming 160-bit data into formats such as 10-bit RGBA, 12-bit RBGA, L16 grayscale, Stereo Field Sequential mode, or indexed color values. Additionally, this hardware integrates the cursor functionality and supports a color index map with up to 32,768 entries.

Capabilities and performance

InfiniteReality delivers a range of sophisticated features, including:

• Multi-sampled anti-aliasing at 8x8
• RGBA color depth reaching up to 48 bits
• Support for 16 overlay planes
• A 24-bit floating-point Z-buffer
• Pixel data sizes ranging from 256 to 1,048 bits
• Stereo visualization enabled through quad buffering

Key performance metrics include:

• Processing 11 million non-lit, depth-buffered, anti-aliased triangle strips (each containing 40 pixels) every second
• Rendering 8.3 million textured, depth-buffered, anti-aliased triangle strips (50 pixels each) per second
• Handling over 7 million lighted, textured, anti-aliased triangles each second
• Managing 800 million trilinear mip-mapped, textured pixels with 16-bit texels and depth buffering per second
• Delivering 750 million trilinear mip-mapped, textured pixels with 16-bit texels and 4x4 sub-sample anti-aliasing every second
• Exceeding 710 million textured, anti-aliased pixels per second
• Displaying up to 300 million pixels per second across one to eight output channels

InfiniteReality2

The term InfiniteReality2 designates the InfiniteReality variant integrated within the Onyx2 system; however, it continued to be marketed under the InfiniteReality name. Launched in late 1996, it retained the core architecture but featured mechanical differences due to the Onyx2’s Origin 2000-style card cage as opposed to the Onyx’s Challenge-based chassis.

With InfiniteReality2, a new interface design was introduced for rack-mounted Onyx2 and subsequent systems. Instead of utilizing FCI cable connections, the boards are inserted into a midplane that accommodates two separate pipelines. This midplane includes eleven slots: slots six through eleven are allocated for the first pipeline (supporting one to four Raster Manager boards), while slots one through four serve the second pipeline (allowing one or two Raster Manager boards). To prevent restrictions on pipeline configurations in fully populated setups, each pipeline employs an independent midplane.

Slot five is reserved for a Ktown board (in Origin 2000 systems) or a Ktown2 board (in Origin 3000 systems), which connects the host system’s XIO link to the Geometry board’s Host Interface Processor ASIC. These boards come equipped with two XIO ports—where the upper port links to the right pipeline and the lower port connects to the left pipeline.

Reality

The Reality is a more economical variant of the InfiniteReality2, engineered to provide comparable performance levels. It incorporates the GE14-2 Geometry Engine board featuring two processors instead of four. Raster Manager options include the RM8-16 and RM8-64 boards, which offer either 16 MB or 64 MB of texture memory alongside 40 MB of raster memory. The Reality supports configurations with one or two Raster Manager boards, allowing up to 80 MB of raster memory when fully outfitted with two RM8-64 boards.

InfiniteReality2E

Debuting in 1998 as an enhancement to InfiniteReality and marketed under the InfiniteReality2 label, the InfiniteReality2E delivered improved performance by replacing the GE14-4 Geometry Engine with the faster GE16-4 board operating at 112 MHz. Additionally, Raster Managers were upgraded to the RM9-64 model running at 72 MHz. These advancements boosted both geometry processing capacity and anti-aliased pixel fill rates. Although succeeded by InfiniteReality3 in 2000, InfiniteReality2E remained available until April 2001.

InfiniteReality3

Introduced in 2000 alongside the Onyx 3000, the InfiniteReality3 system was integrated into both Onyx2 and Onyx 3000 platforms. Its major enhancement involved substituting the RM9-64 Raster Manager with the RM10-256, which featured 256 MB of texture memory—quadrupling the capacity of its predecessor. When fully equipped with four Raster Managers, it offered a total of 320 MB raster memory.

InfiniteReality4

Debuting in 2002 as the successor to InfiniteReality3, InfiniteReality4 supported Onyx2, Onyx 3000, and Onyx 350 systems. This generation represented the last before the shift to ATI FireGL-based UltimateVision graphics in Onyx4. The standout improvement was the RM11-1024 Raster Manager, delivering enhanced capabilities with 1 GB texture memory and 2.5 GB raster memory—amounting to four times and thirty-two times increases respectively over previous models. Configured with four Raster Managers, the system provided 10 GB raster memory; scaling up to sixteen pipelines, it achieved a maximum of 16 GB texture memory and 160 GB raster memory.

Comparison

The following tables illustrate configurations ranging from a single pipeline setup up to sixteen pipelines, except for the Reality model, which utilized only one pipeline.

Hardware

Model	Geometry Engine board	Raster Manager board	Display Generator board	Texture memory (MB)	Raster memory (MB)	Introduced	Discontinued
Reality	GE14-2	RM8-16 or RM8-64	DG5-2 or DG5-8	64	40 to 80	1999-01-01	1999-06-30
InfiniteReality	GE12-4	RM6-16 or RM6-64	DG4-2 or DG4-8	16 to 1,024	80 to 5,120	1996-01-01	1999-03-31
InfiniteReality2	GE14-4	RM7-16 or RM7-64	DG5-2 or DG5-8	16 to 1,024	80 to 5,120	1996-01-26	1999-09-30
InfiniteReality2E	GE16-4	RM9-64	DG5-2 or DG5-8	64 to 1,024	80 to 5,120	2001-01-16	2003-06-27
InfiniteReality3	GE16-4	RM10-256	DG5-2 or DG5-8	256 to 4,096	80 to 5,120	2000-01-01	2003-06-27
InfiniteReality4	GE16-4	RM11-1024	DG5-2 or DG5-8	1,024 to 16,384	2,560 to 163,840	2000-01-01	2003-06-27
InfinitePerformance	V12 Odyssey	XIO	XIO	104 to 1,664	128 to 2,048	2002-01-01	2006-01-01

Performance

Model	Polygons (millions per second)	Pixel fill (millions of pixels per second)	Volume rendering (millions of voxels per second)
InfiniteReality	10.9	–	–
InfiniteReality2	10.9	–	–
Reality	5.5	94 to 188	100 to 200

Model	Polygons (millions/sec)	Pixel fill (millions/sec)	Volume rendering (millions/sec)
'\'InfiniteReality2E\	'13.1 to 210'	'192 to 6,100'	'200 to 6,400'
'\'InfiniteReality3\	'13.1 to210'	'5,600'	'6,800'
'\'InfiniteReality4\	'13.1 to210'	'20,640'	'12,800'

Notes