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SPARC T3

From Alfawiki
Oracle Corporation
Company typePublic
IndustryComputer hardware, Software
PredecessorSun Microsystems
FoundedJune 16, 1977; 49 years ago (1977-06-16) in Santa Clara, California, United States
FounderLarry Ellison, Bob Miner, Ed Oates
Headquarters
Austin, Texas
,
United States
Area served
Worldwide
Key people
Safra Catz (CEO)
ProductsSPARC microprocessors, Database software, Cloud services
OwnerPublic company
Websiteoracle.com

The SPARC T3 microprocessor—originally known as the UltraSPARC T3 and codenamed Rainbow Falls—is a multithreaded, multi-core processor engineered by Oracle Corporation (previously Sun Microsystems). Introduced on September 20, 2010, it is part of the SPARC series and serves as the successor to the UltraSPARC T2.

Performance

The SPARC T3 delivers a substantial increase in throughput, achieving enhanced performance while requiring only half the number of CPU sockets compared to its forerunner. On a single-socket T3-1 setup, its SPEC CINT2006 rate exceeded that of a dual-socket UltraSPARC T2+ T5240 configuration.

When tested under simulated web server workloads, dual-socket SPARC T3 machines outmatched quad-socket UltraSPARC T2+ systems as well as other competing dual- and quad-socket servers from the same era, highlighting its superior scalability and efficiency in enterprise settings.

History

In June 2008, The Register inaccurately reported that the processor would contain 16 cores with 16 threads each; however, a 2009 roadmap later clarified this as 8 threads per core. During the Hot Chips 21 conference, Sun Microsystems announced the processor’s architecture comprising 16 cores and a total of 128 threads.[1][2] The 2010 ISSCC presentation provided further technical insights:

"A 16-core SPARC SoC processor supports up to 512 threads in a glueless 4-way configuration to maximize throughput. It includes a 6 MB L2 cache with a bandwidth of 461 GB/s and a 308-pin SerDes I/O delivering 2.4 Tb/s bandwidth. The design incorporates six clock domains and four voltage domains alongside power management and circuit techniques to optimize performance, power consumption, variability, and yield on the 377mm2 die."[3]

Support for UltraSPARC T3 was officially confirmed in July 2010 through its integration into OpenSolaris. At Oracle OpenWorld on September 20, 2010, the processor was formally introduced as "SPARC T3," omitting the "Ultra" designation. This launch included new hardware platforms and benchmark results claiming industry-leading performance.[4] Comprehensive real-world application benchmarks and full system disclosures further validated its enterprise workload capabilities.[5] Additionally, internationally recognized SPEC benchmarks reinforced its position at the forefront of performance.[6]

Oracle revealed that production of the SPARC T3 utilized a 40 nm manufacturing process.[7]

Features

Key specifications of the SPARC T3 include:

  • Either 8 or 16 CPU cores
  • Each core supports 8 hardware threads
  • A shared Level 2 cache of 6 MB
  • Two integrated coherency controllers
  • Six coherence links featuring 14 unidirectional lanes each
  • Support for SMP configurations up to four sockets without requiring glue logic
  • Four memory channels compatible with DDR3 SDRAM
  • Embedded PCI Express input/output interfaces
  • Dedicated security co-processors per core supporting encryption standards such as DES, 3DES, AES, RC4; hashing algorithms SHA-1, SHA-256/384/512; Kasumi; Galois Field arithmetic; MD5; RSA keys up to 2048 bits; ECC; and CRC acceleration
  • A hardware-based random number generator
  • Dual built-in interfaces for both 1GigE and 10GigE
  • An aggregate throughput capacity of 2.4 terabits per second per socket

Systems

Oracle introduced its SPARC T-series servers with the release of the SPARC T3 processor, succeeding the earlier UltraSPARC T2 and T2 Plus-based SPARC Enterprise models. The updated product range was condensed into four configurations:

  • A single-socket SPARC T3-1 2U rack-mounted server
  • A single-socket SPARC T3-1B blade server
  • A dual-socket SPARC T3-2 server
  • A quad-socket SPARC T3-4 server

Virtualization

Building on virtualization capabilities from earlier T-series chips, the SPARC T3 supports Hyper-Privileged execution mode and can host up to 128 Oracle VM Server for SPARC domains (previously known as Logical Domains), offering robust virtualization functionality.

Performance improvement versus T2 and T2+

The SPARC T3 effectively combines the power of two T2+ processors on a single silicon die, resulting in notable performance gains:

  • Core count doubled to 16 relative to T2 and T2+
  • Twice the number of 10 Gigabit Ethernet ports (2)
  • Crypto accelerator cores increased twofold (16)
  • Broader support for cryptographic algorithms such as DES, Triple DES, AES, RC4, various SHA versions, Kasumi, Galois Field operations, MD5, RSA up to 2048-bit, ECC, and CRC-32
  • Cryptography throughput nearly doubled compared to UltraSPARC T2 Plus
  • Upgraded memory interface from DDR2 to faster DDR3 RAM
  • Overall throughput and memory capacity both doubled
  • I/O bandwidth quadrupled through dual PCIe 2.0 eight-lane interfaces, compared to a single interface in previous models

See also

  • UltraSPARC T1 – The predecessor to the T2 series and Sun's initial chip-multithreaded processor
  • SPARC T4
  1. ↑ Sun's Next-Generation Multi-threaded Processor - Rainbow Falls: Sun's Next Generation CMT Processor
  2. ↑ Two billion-transistor beasts: POWER7 and Niagara 3
  3. ↑ ISSCC 2010
  4. ↑ Cite error: Invalid <ref> tag; no text was provided for refs named oracle.com
  5. ↑ BestPerf blog entries
  6. ↑ BestPerf blog entries
  7. ↑ Cite error: Invalid <ref> tag; no text was provided for refs named datasheet
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