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UNIVAC 1100/90

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Adapted from the English Wikipedia article UNIVAC 1100/90, available under CC BY-SA 4.0Updated 8 August 2025
UNIVAC 1100/2200 series
Company typeComputer systems family
IndustryComputer hardware
PredecessorUNIVAC vacuum tube computers (1101 through 1105)
Founded1962; 64 years ago (1962)
FounderSperry Rand
FateContinued under ClearPath Dorado Series by Unisys Corporation
SuccessorClearPath Dorado Series (Unisys)
Area served
Worldwide
ProductsUNIVAC 1107, 1108, 1108A, 1100/20 series
OwnerSperry Rand (original), Unisys Corporation (current)

The UNIVAC 1100/2200 series represents a family of compatible 36-bit computer systems, initiated by the introduction of the UNIVAC 1107 in 1962 and originally manufactured by Sperry Rand. Currently, this series continues to be maintained under the ClearPath Dorado Series by Unisys Corporation. The solid-state 1107 model succeeded earlier vacuum-tube computer models, although those predecessors were not compatible with the subsequent solid-state versions.

Data formats

  • Fixed-point types, encompassing both integer and fraction categories:
    • Full word – 36 bits using (ones' complement)
    • Half word – two 18-bit segments per word (unsigned or ones' complement)
    • Third word – three 12-bit segments per word (ones' complement)
    • Quarter word – four 9-bit segments per word (unsigned)
    • Sixth word – six 6-bit segments per word (unsigned)
  • Floating point:
    • Single precision – 36 bits consisting of a sign bit, an 8-bit characteristic, and a 27-bit mantissa
    • Double precision – 72 bits comprising a sign bit, an 11-bit characteristic, and a 60-bit mantissa
  • Alphanumeric:
    • FIELDATA – UNIVAC’s proprietary 6-bit character code variant (lacking lowercase), fitting six characters into each 36-bit word
    • ASCII – 9 bits per character (eight utilized), accommodating four characters per 36-bit word

Instruction format

Each instruction is composed of 36 bits divided into these fields:

f (6 bits) - function code (opcode),
j (4 bits) - partial word indicator, J-register reference, or minor function code,
a (4 bits) - register specifier (A, X, or R) or I/O selector,
x (4 bits) - index register (X) specifier,
h (1 bit) - index register increment flag,
i (1 bit) - indirect addressing flag,
u (16 bits) - address or operand specifier.

Registers

Address Register Contents
000 Unused Unused
001 X1 Increment Modifier
... ... Increment Modifier
013 X11 Increment Modifier
014 X12/A0 Overlap (X or A)
... ... Overlap (X or A)
017 X15/A3 Overlap (X or A)
020 A4 Accumulator
... ... Accumulator
033 A15 Accumulator
034 A15+1 Unassigned (A)
... ... Unassigned (A)
037 A15+4 Unassigned (A)
... Executive Protected Executive
101 R1 Special (R)
... ... Special (R)
117 R15 Special (R)
... Executive Protected Executive
177 Executive Protected Executive

The high-speed "general register stack" consists of 128 registers that are mapped within main memory starting at address zero. This collection includes both user and executive versions of the A, X, R, and J registers alongside special executive registers. The table displays user register addresses in octal notation.

There are fifteen index registers designated X1 through X15, sixteen accumulators labeled A0 to A15, and fifteen special-purpose user registers R1 to R15. The four J registers and three staging registers correspond to certain special R registers.

Significantly, the final four index registers (X12 to X15) share storage locations with the first four accumulators (A0 to A3), allowing versatile data interpretation. This overlapping arrangement results in four unassigned accumulators (A15+1 through A15+4), which can only be accessed via memory addressing; however, double-word instructions targeting A15 also affect A15+1.

Vacuum tube machines lacked interoperability

Prior to the UNIVAC 1107, UNIVAC developed a series of vacuum tube computers numbered from 1101 through 1105. These machines differed significantly in design and word length, resulting in incompatibility both among themselves and with the later 1107 models. Each utilized vacuum tube technology and frequently incorporated drum memory as their primary storage medium. Certain models originated from Engineering Research Associates (ERA), which was subsequently integrated into UNIVAC.

The UNIVAC 1101 (also known as ERA 1101) was created by ERA and manufactured by Remington Rand during the 1950s but was never offered commercially. The UNIVAC 1102 was an ERA design commissioned for the U.S. Air Force. Released in 1953, the 36-bit UNIVAC 1103 and its enhanced version, the 1103A (1956), were pioneering commercial computers that utilized core memory rather than the earlier Williams tube. The UNIVAC 1105, introduced in 1958, served as the successor to the 1103A.

The UNIVAC 1104, a 30-bit derivative of the 1103, was developed in 1957 for Westinghouse Electric to support the BOMARC Missile Program. Nevertheless, by the time the missile was deployed in the 1960s, it had been superseded by a more advanced system, the AN/USQ-20 G-40.

UNIVAC 1100 series with compatibility

These models shared an identical architecture and word length, featuring electronics based on transistor technology and later integrated circuits. Initially, they employed core memory—with the exception of the 1110 model which used plated-wire memory—before adopting semiconductor memory around 1975.

1107

Launched in October 1962, the UNIVAC 1107 was Sperry Univac's first solid-state entry in the UNIVAC 1100 lineup. Dubbed the Thin-Film Computer due to its use of thin-film memory for register storage, it represented a significant architectural advancement: a single-address system equipped with up to 65,536 words of 36-bit core memory. Registers resided within a faster thin-film memory consisting of 128 words, facilitating address indexing without incurring cycle time delays. Only thirty-six units were sold.

Core memory came in increments of 16,384 words up to a maximum of 65,536 words split across two banks, each with a cycle time of four microseconds (effectively two microseconds when overlapping instruction fetch and data access). The thin-film memory register stack offered an access time of approximately 300 nanoseconds and enabled sophisticated indexing through high-speed adder hardware. Sixteen input/output channels also utilized thin-film memory for direct-to-memory I/O registers. Execution from unused thin-film locations was not permitted.

Supported peripherals included both UNISERVO IIA and UNISERVO III tape drives compatible with metallic or mylar tape, alongside the FH880 drum memory device providing roughly 300,000 words at a rotational speed of 1800 RPM for spooling and file storage tasks.

The complete system weighed approximately .

Univac supplied a batch processing operating system named EXEC I, while Computer Sciences Corporation developed an optimizing compiler for Fortran IV, an assembler called SLEUTH featuring advanced macro capabilities, and a versatile linking loader.

Cost example

A typical budget for a UNIVAC 1107 system in 1963 included major components such as the central processor priced at $888,750, two-bank core memory costing $798,750, along with various peripherals including card readers and high-speed printers, bringing the total near $3.5 million. Additional expenses covered tape media valued at $300,000 and spare parts amounting to $145,000.

1108

Launched in 1964, the UNIVAC 1108 succeeded the 1107 by replacing thin-film memory registers with integrated circuits and enhancing core memory speed. Notable improvements included two 18-bit base registers that facilitated dynamic program relocation and memory protection, supporting multiprogramming through separate instruction (I-bank) and data (D-bank) memory banks. The introduction of the Processor State Register (PSR) enabled management of storage protection and privileged instruction control via Guard Mode.

The 1108 incorporated new hardware instructions for double precision calculations and double-word operations. It accommodated up to 16 input/output channels. The central processing unit primarily consisted of discrete logic cards connected by wire-wrapped backplanes, while integrated circuits were employed for the 128-word Integrated Control Register stack. Core memory was organized into two 32K modules, totaling 64K words, with a cycle time of 750 nanoseconds.

Shortly after its release in 1965, Sperry Rand introduced the UNIVAC 1108 II (also known as 1108A), which added multiprocessing features supporting up to three CPUs, four memory banks with a total of 262,144 words, and two programmable input/output controllers (IOCs). This design enabled simultaneous execution of five processes: three CPU programs alongside two I/O operations. The instruction set was expanded to include a test-and-set command for CPU synchronization.

Although initial forecasts estimated sales around 43 units, production reached a total of 296 processors. Common setups featured one or two CPUs with multiple I/O channels and two or three core memory cabinets; configurations with three CPUs and four memory cabinets were uncommon due to expense. The IOC cabinet enhanced I/O capacity to handle extensive mass storage requirements, with United Air Lines as a major customer.

The UNIVAC Array Processor (UAP), a dedicated mathematical coprocessor for the 1108A, was manufactured in very limited numbers. It comprised four arithmetic units housed in a separate cabinet and interfaced between two multiprocessor systems, accessing up to four core memory cabinets. Tailored for array-processing tasks such as fast Fourier transforms (FFT), it operated independently from the CPUs and signaled task completion via interrupts. Clients included Shell Oil and Canadian companies Digitech and Gulf Canada for seismic data analysis.

When Sperry Rand transitioned from core memory to semiconductor memory technology, the system was renamed the UNIVAC 1100/20, where the final digit indicated the number of CPUs (for example, 1100/22 represented a dual-CPU configuration).

1106

The early models like the 1107 and initial versions of the 1108 primarily targeted scientific and engineering users, as reflected by the UNIVAC Scientific Exchange (USE) user group within the 1100 Series community. Their batch-oriented operating systems mainly supported FORTRAN and to a lesser degree ALGOL. As commercial computing expanded, these machines struggled to accommodate business workloads typically coded in COBOL. To address this gap, UNIVAC developed the multiprocessor 1108A system along with the EXEC 8 operating system. Since business applications were often limited by I/O throughput rather than CPU performance—resulting in CPU idle times reaching up to 50% in multiprocessor environments—there was demand for a more affordable, lower-performance system tailored for commercial use.

Introduced in December 1969, the UNIVAC 1106 shared physical design and instruction set compatibility with the 1108 but offered reduced costs by supporting configurations with fewer I/O channels. Although capable of multiprocessing, it was seldom supplied with more than two CPUs and did not support IOC hardware. Initial versions of the 1106 operated at roughly half the speed of the 1108; later models employed slower but more economical memory systems. In total, Sperry Univac sold 338 processors within the 1106 product line.

Following Sperry Rand’s adoption of semiconductor memory technology replacing core memory, this model was rebranded as the UNIVAC 1100/10.

  • Note: EXEC 8’s "idle loop" technique minimized core memory consumption by performing operations within CPU-resident memory during I/O waits, thereby optimizing resource utilization.*

1110

Introduced in 1972, the UNIVAC 1110 advanced multiprocessing capabilities by enabling sixteen-way memory access and supporting up to six Command Arithmetic Units (CAUs) alongside four Input Output Access Units (IOAUs). The CAU extended memory addressing from 18 bits to 24 bits, allowing access to as much as 16 million words of memory. Core memory was replaced by plated-wire memory, with each cabinet housing eight separate 8K modules, totaling 64K words, and expandable up to four cabinets. Additional Extended Memory cabinets could be linked via daisy chaining, providing up to one million extra words of storage through either 1108 core or larger, more economical 1106 memory cabinets.

The base setup mandated at least two CAUs and one IOAU, while the full configuration of six CAUs and four IOAUs was exclusively utilized by NASA. Instruction pipelining was introduced with the 1110, permitting simultaneous execution of up to four instructions in different pipeline stages. The IOAU functioned independently from the CAUs, featuring dedicated access paths to both Main and Extended Memory, thus preventing memory cycle conflicts during input/output processes. It supported multiple compatible word channels and contained the Hardware Maintenance Panel, which displayed CAU register information. The system also expanded its instruction set by incorporating 'Byte Instructions.' Components employed high-density connectors and transistor–transistor logic (TTL) integrated circuits, replacing previous discrete logic implementations; the CAU alone contained over 1,000 such cards.

With the transition from plated-wire modules to semiconductor memory, Sperry Rand introduced the UNIVAC 1100/40, where the final digit denoted the number of CPUs. This new Main Memory cabinet included larger static RAM modules of 16K words each, increasing maximum main memory capacity to 524K words. The CAU now supported four base and limit registers for dynamic bank switching—an enhancement over the earlier fixed bank addressing scheme.

Sperry Rand sold a total of 290 units within the 1110 series.

  • Note: TTL integrated circuits utilized ceramic 14-pin dual in-line packages (DIPs) with +5V and ground connections, representing advanced technology as of 1969.*

Semiconductor memory series

In 1975, Sperry Univac introduced a new generation that replaced magnetic core memory with semiconductor-based memory and adopted a revised naming system:

The enhanced 1106 was rebranded as the UNIVAC 1100/10, where the last digit indicated the number of CPUs or CAUs (for example, a two-processor model was designated 1100/12). Similarly, the upgraded 1108 became known as the UNIVAC 1100/20.

The improved 1110 was released under the name UNIVAC 1100/40, featuring a new Type 7030 solid-state (static RAM) Memory Cabinet with a capacity of 131K words that replaced the older Type 7015 Plated-Wire Memory cabinet holding 64K words. This effectively doubled Main Storage from 262K to 524K words. Additionally, the Type 7013 Core Memory Cabinet (131K) was superseded by a Solid-State Memory Cabinet utilizing Intel 1103A dynamic RAM technology.

The UNIVAC 1100/80, unveiled in 1979, sought to integrate features from both the 1100 and 494 systems. It incorporated a high-speed cache known as the Storage Interface Unit (SIU), available with either 8K or optional 16K words of 36-bit storage positioned between CAU(s)/IOU(s) and slower Main Memory. Initially supporting configurations with up to two CAUs and two IOUs, subsequent versions expanded capacity to four of each. The SIU enabled logical segmentation of multiprocessor setups into independent systems running separate operating systems.

The CAU executed instructions compatible with both the 36-bit 1100 series and the earlier 30-bit 490 series, utilizing Emitter-Coupled Logic (ECL) chips for registers that eliminated parity checking during read/write cycles. The modular IOU accommodated various Channel Modules tailored for diverse I/O requirements including Word Channels, Block Multiplexers, and Byte Channels. The SIU housed a Control/Maintenance Panel containing a BC/7-based minicomputer responsible for microcode loading and system diagnostics. ECL logic was implemented on high-density multilayer printed circuit boards powered by specialized -2 volt supplies and motor-driven 400 Hz power sources to enhance reliability.

A premium 1100/84 multiprocessor configuration included four CPUs, two IOUs, two SIUs each with 16K words, over two million words of Main Memory along with maintenance units, power supplies, and consoles; its list price reached $5.4 million in October 1980. Rental and leasing options were available, with discounts commonly offered to large-scale or government purchasers.

Also launched in 1979 was the UNIVAC 1100/60, which replaced prior models such as the 1100/10 and 1100/20. Offered in single-processor (1100/61) and dual-processor (1100/62) variants, it featured custom-designed Sperry microprocessor integrated circuits. Main Storage per CPU ranged from 524K up to one million forty-eight thousand words (1,048K), complemented by optional semiconductor buffer storage and modular I/O supporting block and word channels. A System Support Processor facilitated diagnostic operations and console management.

An enhanced 1100/62 Model E1 medium-performance multiprocessor comprised two CPUs equipped with buffer storage; dual IOUs featuring block multiplexers and word channel modules; more than one million words of Main Storage; system support processors; consoles; and maintenance equipment. Priced at $889,340 in March of 1980, this model was available for rent or lease accompanied by maintenance contracts; discounts were standard for major or governmental clients.

Introduced in 1981, the UNIVAC 1100/70 represented an improved iteration based on the architecture of the 1100/60 design and replaced earlier systems built around the older 1110-based 1100/40.

The UNIVAC 1100/90, debuting in 1982 as the largest and final model in this line, supported configurations with up to four processors and four I/O units. It uniquely employed liquid cooling technology.

The Sperry Integrated Scientific Processor (ISP) was launched as an add-on module specifically for use with the 1100/90 system.

SPERRY 2200 series

The UNIVAC brand was retired by Sperry Corporation in 1983.

Unisys 2200 series

Following the 1986 merger of Sperry Corporation and Burroughs Corporation, the resulting entity was named Unisys, prompting a rebranding of its system lines. Although these systems maintained a common architectural foundation, their performance levels varied.

Unisys ClearPath IX series

In 1996, Unisys unveiled the ClearPath IX series, a consolidated platform designed to support either the traditional 1100/2200 architecture (ClearPath IX) or the architecture of the Burroughs large systems (ClearPath NX). These platforms share most hardware elements except for their ASIC-based CPUs. The lineup incorporated not only IX and NX processors but also Intel Xeon and briefly Itanium chips. This approach was intended to modernize the product line while facilitating a seamless migration for existing customers using the older architectures.

Deployments

A UNIVAC 1107 was employed in a traffic management system for metropolitan Toronto as early as 1964 to automate vehicle flow analysis.

In Sweden, a national vehicle registration system operated from the early seventies to the early eighties, utilizing UNIVAC 1106 front-end processors linked with UNIVAC 418 units. By March of 1979, this infrastructure included multiple UNIVAC 1106-II machines, expanded memory and storage arrays, communication processors, and terminals servicing police forces and administrative personnel.

The system underwent an upgrade to a UNIVAC 1100/60 platform in 1981 and continued evolving through further enhancements to UNISYS XPC-L and subsequent models, demonstrating sustained commitment to scalable computing solutions.

See also

External links

Related profiles

UUNIVAC 1100/2200 seriesUUNIVAC 1105UUNIVAC 1103UUNIVAC 9200
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