UltraSPARC III
| Industry | Computer hardware, Software |
|---|---|
| Founded | February 24, 1982 in Santa Clara, California, United States |
| Founder | Vinod Khosla, Andy Bechtolsheim, Scott McNealy, Bill Joy |
| Fate | Acquired by Oracle Corporation in 2010 |
| Headquarters | Santa Clara , United States |
| Products | UltraSPARC microprocessors, Solaris OS |
The UltraSPARC III, known internally as "Cheetah", is a microprocessor that implements the SPARC V9 instruction set architecture (ISA). It was developed by Sun Microsystems and manufactured by Texas Instruments. Launched in 2001, this chip operates at clock speeds ranging from 600 to 900 MHz and was followed by the UltraSPARC IV in 2004. The chief architect behind its design was Gary Lauterbach.
History
Initially unveiled at the 1997 Microprocessor Forum with plans for a 1999 release, the UltraSPARC III experienced delays that postponed its launch until 2001. Despite this setback, it received the Analysts' Choice Award for Best Server/Workstation Processor of 2001 from Microprocessor Report, largely due to its sophisticated multiprocessing features.
Description
The UltraSPARC III is a superscalar processor that executes instructions in order, tailored specifically for shared memory multiprocessing. Its design incorporates an integrated memory controller alongside a dedicated bus for multiprocessing, both aimed at boosting parallel processing efficiency.
Instruction fetching can retrieve up to four instructions per cycle from the instruction cache, while up to six decoded instructions may be issued simultaneously to execution units, depending on resource availability. The execution units include two arithmetic logic units (ALUs), a load/store unit, and two floating-point units (FPUs). One ALU is responsible for simple integer operations and loads; one FPU handles basic floating-point tasks such as addition; the other FPU manages more complex calculations including multiplication, division, and square root operations.
Cache
This processor utilizes separate primary caches: a 32 KB instruction cache and a 64 KB four-way set-associative data cache with 32-byte line size. Its external L2 cache can reach up to 8 MB and connects via a dedicated 256-bit bus running at speeds up to 200 MHz, providing a maximum bandwidth of 6.4 GB/s. The L2 cache uses synchronous static RAM clocked at up to 200 MHz, while its on-chip tags operate at the processor’s frequency to increase tag access bandwidth. This configuration supports effective cache coherency traffic critical for multiprocessor environments. The L2 cache tags require about 90 KB of storage.
External interface
The chip’s external interface consists of a 128-bit data bus combined with a 43-bit address bus, both operating at 150 MHz. This data bus facilitates access to memory on other processors and shared input/output devices rather than local memory.
Memory controller
An integrated memory controller within the UltraSPARC III utilizes a dedicated 128-bit bus running at 150 MHz and supports up to 4 GB of local memory. This integration minimizes latency to improve overall performance, contrasting with other UltraSPARC variants where the memory controller primarily serves cost-reduction purposes.
Physical
Containing approximately 16 million transistors—with roughly three-quarters allocated to caches and tags—the UltraSPARC III was initially produced by Texas Instruments using a 0.18 μm CMOS fabrication process featuring six layers of aluminum interconnects. In 2001, manufacturing shifted to a more advanced 0.13 μm process, enabling clock frequencies between 750 and 900 MHz. The die employs Controlled Collapse Chip Connection packaging technology—the first Sun microprocessor to adopt this method—with most solder bumps arranged around the periphery on a 1368-pad land grid array (LGA) package.
UltraSPARC III Cu
The UltraSPARC III Cu (also known as "Cheetah+") represents an improved version of the UltraSPARC III, operating at frequencies ranging from 1002 to 1200 MHz. Manufactured by Texas Instruments, this processor features a 232 mm2 silicon die produced using a 0.13 μm CMOS technology with seven layers of copper interconnects. It is packaged within a ceramic LGA housing containing 1,368 pads.
UltraSPARC IIIi
Released in 2003, the UltraSPARC IIIi ("Jalapeño") targets workstations and entry-level servers supporting one to four processors, with clock speeds between 1064 and 1593 MHz. This model integrates both an on-chip L2 cache and a memory controller, enabling four-processor configurations through a glue-less system bus optimized for multiprocessing. The chip comprises 87.5 million transistors on a 178.5 mm2 die fabricated by Texas Instruments utilizing a 0.13 μm CMOS process that incorporates seven-layer copper metallization alongside low-k dielectric materials.
Its single unified L2 cache is sized at 1 MB and operates at half the CPU’s clock frequency, exhibiting a six-cycle latency and two-cycle throughput; the total load-to-use latency measures 15 cycles. The cache architecture is physically indexed and tagged, four-way set-associative, with tags protected by parity and data safeguarded by ECC—featuring 36 error-correcting code bits per 64-byte line to allow single-bit error correction and detection of multiple-bit errors. The SRAM cells occupy approximately 2.76 μm2, collectively comprising 63 million transistors.
The integrated memory controller accommodates between 256 MB and 16 GB of DDR-I SDRAM running at 133 MHz across a 137-bit bus (128 data bits plus nine ECC bits), achieving a maximum bandwidth of 4.2 GB/s. Designed for four-way multiprocessing, the Jbus facilitates interconnection of up to four CPUs via a multiplexed 128-bit address/data bus operating at either one-half or one-third of the processor’s clock speed.
UltraSPARC IIIi+
The UltraSPARC IIIi+, internally known as "Serrano," was an upgraded iteration of the UltraSPARC IIIi planned for launch in late 2005 but ultimately cancelled that same year in favor of newer models such as the UltraSPARC IV+, UltraSPARC T1, and UltraSPARC T2. This cancellation was officially announced on August 31, 2006. The proposed enhancements included clock frequencies approaching 2 GHz, an expanded on-die L2 cache of 4 MB, support for DDR-333 SDRAM, and fabrication using a more advanced 90 nm process technology.
Successors
Following the UltraSPARC III series, the UltraSPARC IV line emerged as its successor by integrating dual UltraSPARC III cores onto a single chip with increased operating frequencies. The physical package remained largely consistent with its predecessor, differing by only one pin, which simplified board design and enabled easier system upgrades. Certain systems equipped with UltraSPARC III processors were capable of upgrading to UltraSPARC IV CPU modules.