PA-8000

Hewlett-Packard
Company type	Public
Industry	Information technology, computer hardware
Founded	January 1, 1939; 87 years ago in Palo Alto, California, United States
Headquarters	Palo Alto, United States
Products	PA-8000 microprocessor series, HP 9000 workstations and servers, HP 3000 servers
Owner	Hewlett-Packard Enterprise (spin-off)
Website	www.hpe.com

The PA-8000 (PCX-U), internally known as Onyx, is a microprocessor created and manufactured by Hewlett-Packard (HP) that implements the PA-RISC 2.0 instruction set architecture (ISA). This design was entirely new, with no components carried over from previous PA-RISC processors. It was unveiled on 2 November 1995, with initial distribution limited to members of the Precision RISC Organization (PRO). The PA-8000 was not available for general commercial sale, being exclusive to PRO partners. Later iterations in the PA-8x00 series (from PA-8200 through PA-8900) were developed based on this processor's core architecture.

The PA-8000 served as the central processing unit for:

HP's HP 9000 and HP 3000^[1] workstation and server platforms
The NEC TX7/P590 server
Fault-tolerant servers from Stratus Technologies known as Continuum

Description

As a four-way superscalar microprocessor, the PA-8000 supports out-of-order execution alongside speculative execution techniques.^[2]^[3] These capabilities represented a significant shift from earlier PA-RISC designs, which primarily depended on simpler microarchitectures combined with elevated clock frequencies to achieve performance gains.^[4]

Instruction fetch unit

The processor’s front-end pipeline consists of four stages, fetching four instructions from the instruction cache during the initial two stages.^[4] The instruction fetch unit (IFU) encompasses components such as the program counter, a branch history table (BHT), a branch target address cache (BTAC), and a four-entry translation lookaside buffer (TLB).^[2]^[4] The TLB handles virtual-to-physical address translation for accessing the instruction cache, consulting the main TLB upon encountering misses.^[2]

Branch prediction

Branch prediction in the PA-8000 operates by employing either static or dynamic strategies, with the method determined by a flag within each TLB entry.^[2] Static prediction assumes backward branches are taken and forward branches are not, also integrating compiler-generated hints embedded within instructions.^[2]^[4]

Dynamic prediction utilizes a 256-entry BHT, where each slot is a three-bit shift register maintaining branch history. The processor uses a majority vote mechanism: if most bits are set, the branch is predicted as taken; if not, it is predicted as not taken.^[2] Incorrect predictions result in a five-cycle penalty.^[4] Although capable of processing two branches per cycle, only one branch outcome can update the BHT due to its single-port architecture.^[3]

When branches are predicted correctly, a two-cycle bubble occurs because the target address must be computed before fetching can continue.^[4] To reduce this delay, the PA-8000 employs a fully associative BTAC with 32 entries that caches target addresses of branches predicted taken. Upon encountering a recurring predicted-taken branch, its target address is forwarded immediately to the instruction cache, minimizing wait times.^[2]

The BTAC only stores targets for branches predicted as taken; entries corresponding to branches predicted not taken are removed. When the cache reaches capacity, entries are replaced using a round-robin scheme.^[2]

Instruction cache

The external instruction cache ranges in size from 256 KB up to 4 MB. To accelerate subsequent decoding, each instruction is pre-decoded by appending five additional bits. The cache employs a direct-mapped design for straightforward access and communicates through a 148-bit wide bus. Cache tags reside externally, and synchronous SRAMs (SSRAMs) are utilized for storage.

Decode, and the instruction reorder buffer

Instruction decoding occurs during the third pipeline stage, followed by entry into the instruction reorder buffer (IRB) at stage four. The IRB facilitates register renaming, supports out-of-order and speculative execution, and temporarily holds results until instructions retire. It controls instruction issue during stage five.

The IRB consists of two separate buffers, each with 28 entries: one dedicated to integer and floating-point instructions, the other handling load/store operations. Branch instructions and certain system-level commands populate both buffers. Each buffer can accept up to four instructions per cycle and issue a maximum of two to the execution units.

Execution

Execution commences at stage six across ten functional units. Integer operations, excluding multiplication, are processed by two ALUs along with two shift/merge units, all featuring single-cycle latency; their results are written back in stage seven.

Floating-point calculations and integer multiplication are handled by two pipelined fused multiply–accumulate (FMAC) units plus two divide/square-root units. The FMAC units exhibit a three-cycle latency without intermediate rounding between multiply and accumulate phases: multiplication takes place in stage six, addition in seven, rounding in eight, and writeback in nine. Divide and square-root units operate without pipelining with a 17-cycle latency; they issue one instruction each cycle but run concurrently with FMAC units.

Load and store commands utilize two specialized address adders.

Translation lookaside buffer

The translation lookaside buffer (TLB) is dual-ported and fully associative with 96 entries, capable of translating two virtual addresses per cycle for both instruction fetches and data accesses. Upon misses in the IFU TLB, this secondary TLB provides translations while giving priority to load/store address translation over instruction translation. It supports page sizes ranging from 4 KB up to 16 MB in powers-of-four increments.

Data cache

The PA-8000 incorporates a data cache that can be sized up to 4 MB and is dual-ported through two separate banks. This design allows for two simultaneous reads or writes per cycle unless both operations target the same bank, which leads to conflicts. Each bank connects via a dedicated 64-bit bus, with external cache tags duplicated to enable independent access. Like the instruction cache, it is direct-mapped and constructed using SSRAM technology.

Runway bus

The external interface utilizes the Runway bus, a 64-bit multiplexed bus carrying both address and data signals. The PA-8000 supports a 40-bit physical address, enabling addressing of up to 1 TB of physical memory.

Physical

The PA-8000 chip contains approximately 3.8 million transistors on a die measuring 17.68 mm by 19.10 mm (337.69 mm²). Manufactured by HP using their 0.5 μm CMOS-14C process—a refinement achieving a 10% gate size reduction from CMOS-14—it features 704 signal solder bumps along with 1,200 power/ground bumps. The package is a flip chip alumina ceramic land grid array (LGA) with 1,085 pads, operating at a voltage of 3.3 V.

PA-8200

Introduced in June 1997, the PA-8200 (PCX-U+), also known by its codename Vulcan, represented an advancement over the PA-8000, operating at frequencies between 200 and 240 MHz and primarily competing against the Alpha 21164. This processor enhanced branch prediction by increasing the Branch History Table (BHT) entries fourfold to 1,024, utilizing a two-bit prediction scheme alongside a write queue capable of recording two branch outcomes per cycle. The Translation Lookaside Buffer (TLB) was expanded from 96 to 120 entries to minimize miss rates. Minor circuit modifications allowed for improved clock speeds without increasing the die size, which remained consistent with the PA-8000 by utilizing previously unused silicon areas. Manufacturing continued on the CMOS-14C fabrication process.

PA-8500

Released in late 1998, the PA-8500 (PCX-W), codenamed Barracuda, marked a significant step forward from the PA-8200, delivering clock speeds ranging from 300 to 440 MHz with design targets up to 500 MHz. Its primary improvements included higher operating frequencies and integration of primary caches on-chip, made possible by transitioning to a 0.25 μm CMOS fabrication technology. The core dimensions were reduced to 10.8 mm by 11.4 mm (123.12 mm²), freeing silicon area for cache inclusion.

This processor featured a 512 KB instruction cache alongside a 1 MB data cache, doubled the BHT capacity to 2,048 entries, and enlarged the TLB to hold 160 entries. The revised Runway bus operated at 125 MHz with double data rate transfers, achieving peak bandwidth near 2 GB/s (approximately 1.6 GB/s effective).

Fabrication was handled by Intel Corporation using a five-level aluminum interconnect CMOS process at 0.25 μm scale. The chip contained around 140 million transistors on a die measuring 21.3 mm by 22.0 mm (468.6 mm²) and ran at a lowered voltage of 2.0 V. HP outsourced manufacturing as they halted further upgrades beyond their CMOS-14C fabs.

The packaging shifted to a more compact 544-pad land grid array (LGA), enabled by on-die cache integration which eliminated the need for external cache buses and associated I/O pads.

PA-8600

The PA-8600 (PCX-W+), bearing the codename Landshark, was an improved iteration of the PA-8500 introduced in January 2000 and targeted for mid-year release. It achieved higher clock rates between 480 and 550 MHz through microarchitectural refinements including adoption of a quasi-least recently used (LRU) policy for instruction cache replacement. Fabrication responsibilities remained with Intel.

PA-8700

Unveiled in August 2001, the PA-8700 (PCX-W2), known as Piranha, operated within a frequency range of 625 to 750 MHz. Key upgrades encompassed data prefetching capabilities, implementation of a quasi-LRU replacement policy for the data cache, and expansion of physical addressing to 44 bits—supporting up to 16 TB of memory. Instruction and data caches were increased by half compared to predecessors, reaching sizes of 0.75 MB and 1.5 MB respectively. IBM Microelectronics manufactured this processor using a 0.18 μm silicon on insulator (SOI) CMOS process featuring copper interconnects and low-κ dielectric materials.

PA-8700+

Debuting in mid-2002, the PA-8700+ further refined the architecture of its predecessor, pushing clock speeds up to 875 MHz.

PA-8800

The PA-8800, codenamed Mako, arrived in 2004 as a dual-core successor to the PA-8700+, powering HP's HP 9000 C8000 workstations and Superdome server platforms. Operating frequencies included options at 0.8, 0.9, and 1.0 GHz, this model integrated two modified PA-8700+ cores on a single die, each equipped with reduced-size instruction and data caches of 768 KB to accommodate dual-core placement.

Improvements featured enhanced branch prediction mechanisms along with a large external unified secondary cache of 32 MB offering bandwidth up to 10 GB/s and latency around 40 cycles. This L2 cache was four-way set-associative, physically indexed and tagged with a line size of 128 bytes, implemented through four separate Enhanced SRAM (ESRAM) chips—dynamic RAM designed with SRAM interfaces—and governed by an on-chip controller utilizing ECC-protected tags.

The front side bus was shared with Intel’s McKinley Itanium processor family, providing bandwidth of approximately 6.4 GB/s and compatibility with HP’s Itanium chipset zx1.

Manufactured by IBM using a 0.13 μm SOI process incorporating copper interconnects and low-κ dielectrics, this chip contained roughly 300 million transistors—of which about 25 million were dedicated to logic—on a die measuring approximately 365.8 mm². Packaging consisted of a ceramic ball grid array mounted on a printed circuit board alongside four ESRAM modules forming an integrated module similar in concept to early Itanium processors.

PA-8900

The PA-8900, known by the codename Shortfin, represented an evolution of the PA-8800 and was the final microprocessor developed within the PA-RISC family, launched on 31 May 2005. This processor was utilized in HP 9000 servers as well as the C8000 workstation, with clock speeds ranging from 0.8 GHz up to 1.1 GHz. Despite some speculation, it was not simply a die shrink of its predecessor, the PA-8800. Notably, the Level 2 cache capacity was increased to 64 MB—twice the previous size—offering reduced latency alongside improved mechanisms for error detection and correction. The chip employed the McKinley system bus and maintained compatibility with Itanium 2 chipsets such as the HP zx1. While its microarchitecture remained unchanged, the floating-point unit and on-chip cache circuits were reengineered to lower power usage, resulting in an approximate power dissipation of 35 W per core at 1.0 GHz.