Broadway (processor)
| Company type | Central processing unit |
|---|---|
| Industry | Semiconductor, Video game hardware |
| Predecessor | Gekko (CPU) |
| Founder | IBM |
| Headquarters | East Fishkill, New York and Bromont, Quebec , United States and Canada |
| Products | 32-bit PowerPC CPU for Nintendo Wii |
| Parent | IBM |
Broadway refers to the 32-bit central processing unit (CPU) implemented in Nintendo's Wii gaming system. Created by IBM, this processor was originally fabricated using a 90 nm SOI manufacturing technique before shifting to a more advanced 65 nm SOI process for improved efficiency.
According to IBM, Broadway achieves a 20% reduction in power consumption compared to its forerunner, the 180 nm Gekko chip found in the GameCube. Production took place at IBM’s semiconductor plant in East Fishkill, New York—now under GlobalFoundries ownership—with subsequent bonding, assembly, and testing carried out at IBM’s facility in Bromont, Quebec. While official information is sparse, unofficial sources suggest Broadway is architecturally based on Gekko and operates at a clock speed 50% higher, reaching 729 MHz.
The design of Broadway closely mirrors IBM’s commercial PowerPC 750CL, introduced in 2006 and available with clock rates between 400 MHz and 1000 MHz. This similarity enabled Nintendo to capitalize on IBM’s existing technology while tailoring the processor for enhanced power efficiency and performance aligned with the Wii’s target audience.
Specifications
- Initially manufactured using a 90 nanometer process, later refined to 65 nm in 2007
- Features a superscalar, out-of-order execution PowerPC core customized specifically for the Wii
- Employs IBM’s silicon on insulator (SOI) fabrication technology
- Maintains backward compatibility with the Gekko CPU
- Runs at a frequency of 729 MHz
- Contains two 32-bit integer arithmetic logic units (IU1 and IU2) with four pipeline stages each
- Equipped with a 64-bit floating-point unit (FPU) featuring seven pipeline stages and support for paired singles (2×32-bit SIMD)
- Incorporates specialized units including Branch Prediction Unit (BPU), Load-Store Unit (LSU), System Register Unit (SRU), Memory Management Unit (MMU), and Branch Target Instruction Cache (BTIC)
- Extends the PowerPC750 instruction set with roughly 50 additional SIMD instructions optimized for 3D graphics processing
- Houses a total of 64 kB L1 cache split evenly between instruction and data caches (32 kB each)
- Includes a 256 kB L2 cache
- Delivers performance up to 2.9 GFLOPS
External bus
- Features a 64-bit wide bus
- Operates at a clock rate of 243 MHz
- Provides bandwidth capacity of 1.944 gigabytes per second