HP 2100

Hewlett-Packard 2100 series

Company type	Product line
Industry	Computer hardware
Predecessor	Data Systems Inc (DSI)
Founded	1966 (1966)
Founder	Hewlett-Packard
Defunct	1990 (1990)
Fate	Discontinued
Headquarters	Cupertino, California , United States
Area served	Worldwide
Products	16-bit minicomputers (2116 series, 2100 series, 21MX series)

The HP 2100 series comprised 16-bit minicomputers manufactured by Hewlett-Packard from the mid-1960s through the early 1990s. Over a span of 25 years, tens of thousands of units were sold, placing HP as the fourth-largest minicomputer supplier during the 1970s.

The lineage began with Data Systems Inc (DSI), whose DSI-1000 model formed the basis of HP's entry after acquiring DSI in 1964 and folding it into their Dymec division. The first iteration, the 2116A, was introduced in 1966 and utilized integrated circuit technology alongside magnetic-core memory. Subsequent variants from A to C expanded memory capacity and offered various expansion configurations. Meanwhile, more affordable models such as the 2115 and 2114 were developed, eventually superseded by the HP 2100 series in 1971. In 1974, this line evolved into the 21MX series featuring semiconductor memory.

This family was also marketed under the HP 2000 brand, which integrated a 2100-series processor with specialized hardware to support multi-user time-sharing operation running BASIC. Throughout the 1970s, HP Time-Shared BASIC gained traction, powering numerous early BASIC applications including the famed Star Trek game. The People's Computer Company published software compatible with these HP 2000 systems.

With the arrival of the HP 3000 in 1974 targeting higher-end markets, the original line was repositioned. By 1977, it was rebranded as HP 1000, emphasizing real-time computing capabilities. A major redesign appeared in 1979 with the 1000 L-Series, which employed CMOS large scale integration technology and introduced a tower-style enclosure; however, this change sacrificed backward compatibility with prior expansion cards. The final iteration, known as the A-series, delivered processing speeds surpassing 1 MIPS, culminating in the release of the A990 model in 1990.

Origins

In 1956, HP founded Dynac to pursue projects beyond its main business focus. Due to trademark conflicts, this entity was renamed Dymec in 1958 and became an internal division by 1959; it was later designated the Palo Alto Division in 1967.

Initially engaged in producing various components for HP, Dymec gradually transitioned into assembling test instrumentation. In 1964, engineers Kay Magleby and Paul Stoft investigated using Digital Equipment Corporation's PDP-5 and PDP-8 machines as controllers but found these unsuitable for their requirements. Attempts to acquire Digital Equipment Corporation were unsuccessful due to management issues.

Searching for alternatives, David Packard identified Data Systems Inc. (DSI), then owned by Union Carbide. Although initially doubtful about minicomputers’ potential, Packard obtained approval by framing the device as an "instrument controller." Following HP's acquisition of DSI in 1964, four original DSI employees joined HP personnel at Dymec. Eventually, this computer group relocated to Cupertino, California, forming what became known as the Cupertino Division.

First models

Under Magleby's leadership, development culminated in the design of the 2116A, which was unveiled at the November 1966 Joint Computer Conference in San Francisco. As one of the earliest minicomputers with a 16-bit architecture, it stood out for its modular design and support for real-time computing. The sizable chassis could accommodate up to sixteen expansion cards internally and expand to forty-eight via an external cage.

At launch, a suite of twenty instrumentation cards was available covering functions such as counters, nuclear scalers, electronic thermometers, digital voltmeters, AC/ohms converters, data amplifiers, and input scanners. Additional cards provided interfaces for peripherals including tape drives, printers, punched card readers, and paper tape devices. Real-time operation was facilitated by fixed-position interrupt vectors, each assigned to specific slots to invoke corresponding device drivers promptly.

Market feedback revealed stronger demand within business-oriented data processing rather than instrumentation sectors. This led to introduction of the cost-effective 2115A in 1967 featuring fewer expansion slots aimed at commercial users. The subsequent 2114A model appeared in 1968 with only eight slots and incorporated an internal power supply. Both models omitted some DMA controls and mathematical operations present on the 2116 and operated at reduced speeds.

Early models utilized core memory combined with a hardwired CPU:

• 2116A: Operating at a 10 MHz clock rate with a cycle time of approximately 1.6 μs; standard configuration included 4k words of memory expandable internally to 8k or externally up to 16k; chassis contained sixteen I/O slots expandable externally; weight ; released November 1966 as HP’s first computer employing integrated circuits.
• 2116B: Added capability for up to 32k memory expansion; maintained similar weight; introduced September 1968.
• 2116C: Utilized smaller core memory modules permitting full 32k capacity within main chassis; launched October 1970.
• 2115A: A budget variant lacking DMA and certain math functions; featured eight I/O slots; clocked at 8 MHz with a cycle time near 2.0 μs; weighed , plus external power supply (~); debuted November 1967.
• 2114A: Simplified version of the 2115 incorporating a redesigned front panel with non-mechanical touch switches and an internal power supply; weight ; released October 1968.
• 2114B: Enhanced model introducing a single DMA channel and illuminated push-buttons on front panel; introduced November 1969.
• 2114C: Similar to B but supported up to a maximum of 16k memory; launched October 1970.

HP 2000

In November 1968, Hewlett-Packard introduced the 2000A Timeshare System, later renamed HP 2000/Access. This system was built upon the 2116B architecture, featuring an expanded 8k core memory, and operated using HP Time-Shared BASIC. It employed a separate 2114 unit functioning as a terminal server. The T-S BASIC environment supported multiple user profiles, enabling up to 16 users to operate concurrently.

Subsequent iterations, labeled B through F, incorporated upgraded central processing units. For instance, the 2000F combined a 2100S as its primary CPU and storage controller alongside a 2100A terminal server capable of managing up to 32 serial terminals. Models B, C, and F were designed as dual-processor configurations.

Although the system was costly—the 2000F priced at $105,000 in 1974 (equivalent to approximately $ in current value)—it was the first minicomputer to provide time-shared BASIC, securing significant market acceptance during the early to mid-1970s.

2100

Throughout the 1970s, the 2100 series underwent continuous development with new models that preserved software compatibility and expansion options from the original 2116 design.

In early 1970, Fred Allard devised an innovative magnetic-core memory system utilizing smaller cores and a single sense/inhibit line. This advancement allowed for an 8 kW memory module on a single expansion card and was first implemented in the 2116C models.

The introduction of the 2100A in 1971 marked the replacement of the entire 211x family. This model featured microcode-programmable CPU enhancements such as hardware multiply/divide capabilities and basic memory protection that generated high-priority interrupts. Additionally, a two-channel DMA controller enhanced data throughput, with an optional floating-point unit available. The chassis size was reduced due to an early adoption of switched-mode power supply technology.

By 1972, Hewlett-Packard had delivered approximately 4,500 minicomputers, establishing itself as a prominent market competitor. That year also saw the consolidation of the Mountain View and Cupertino Divisions into the Data Systems Division (DSD). Facing difficulties with the HP 3000 project, Paul Ely was appointed head of this division in early 1973. Sales of the 2100 series remained strong: the shipment milestones included the 6,000th unit in August 1973, the 8,000th in February 1974, and the 10,000th by February 1975. The series was officially retired in 1978.

• 2100A: Typically equipped with 4 kW memory expandable up to 32 kW; featured fourteen I/O slots extendable to forty-five; released in 1971.
• 2100S: A bundled version of the 2100A including floating-point support, a time base generator for time-dependent hardware interfacing, and a teleprinter interface card; introduced in 1973.

21MX

In 1972, HP transitioned from core memory to using 4kbit SRAM chips. These SRAM components were twice as fast and physically smaller than core memory, enabling machines with up to 32kword capacity housed within a form factor similar to the earlier 2114 models. Since initial availability of true 4kbit SRAMs was limited, early versions utilized either slower 1kbit SRAM or core memory from previous models. To mitigate potential delays, HP collaborated closely with semiconductor manufacturers such as Intel, Mostek, Motorola, and Texas Instruments, all planning to supply suitable parts by late 1974.

Memory expansion through external chassis allowed capacities reaching into megaword territory; however, CPU addressing remained limited to fifteen bits restricting systems to a maximum of 32kwords. To overcome this constraint for larger configurations, HP developed the "Dynamic Mapping System" (DMS), which extended addressing capability to twenty bits and supported up to one million forty-eight thousand five hundred seventy-six words.

This advancement facilitated the release of the 21MX series in 1974—named after its "21-M" processor and "21-X" memory controller components that decoupled CPU and memory management for greater flexibility in employing various types of four-kilobit SRAM chips. Systems shipped with memories from Motorola or Texas Instruments and could mix these within a single machine; however, higher-density Mostek-based memories required swapping out controllers.

The introduction of the 21MX series effectively replaced all prior models in the 2100 lineup by that year. Utilizing high-density components enabled support for memory sizes up to approximately 1.2 megabytes. A CPU upgrade released in 1976 introduced the "21MX E-Series," which doubled processing speed compared to the original "M-Series." The product line offered configurations ranging from four up to fourteen slots.

Equipped with a memory management unit and capable of expanding semiconductor memory up to one megaword, these systems employed red LED indicators on their front panels instead of incandescent bulbs for improved reliability.

• M-series – models include 2105A, 2108A, and 2112A (distinguished by blue front panels)
• E-series – models such as 2109A and 2113A (featuring yellow panels; 'E' denotes extended)
• F-series – includes models like 2111F and 2117F (red panels; 'F' indicates floating-point processor housed separately)

The series operated under HP's RTE real-time operating system. Initial versions were large rackmount units roughly refrigerator-sized with front-panel lights and switches; subsequent designs incorporated compact one-chip processors intended for desktop use alongside console terminals.

Later L and A series variants introduced HP-IB interface support but removed front-panel LED indicators. Despite attempts to improve real-time performance through installable cards on newer systems, RTE-A operating system did not achieve parity with RTE running on the original 21MX—a critical reason why companies requiring precise process control over equipment such as pumps, heaters, valves, and motors continued relying on these systems.

1000 series

By the end of 1977, the product line was rebranded as "HP 1000," dividing into two branches: the "HP 1000 M-Series" and "HP 1000 E-Series." The following year, 1978, saw the release of the "HP 1000 F-Series," essentially an E-Series model enhanced with a floating point processor. This achievement elevated HP to become the fourth-largest producer of minicomputers, trailing behind DEC, IBM, and Data General.

The "HP 1000 L-Series," introduced in 1980, featured a processor utilizing HP's silicon on sapphire (SOS) technology with large-scale integration. Its expansion cards incorporated dedicated processors that accessed main memory directly and managed input/output tasks autonomously, improving overall system performance but resulting in incompatibility with previous versions. Notably, earlier models did not include a memory management unit.

In 1982, the L-Series was succeeded by the "HP 1000 A-Series," equipped with the "Lightning" CPU delivering 1 MIPS and the more powerful "Magic" CPU reaching speeds up to 3 MIPS. This series offered configurations ranging from desk-side towers to multiple rack-mounted formats. The entry-level A400 was introduced in 1986, while the top-tier A990 appeared in 1990; both supported memory capacities up to 32 MB.

Prominent models comprised:

• 1981 A600 – Am2900 bit-slice CPU operating at 1 MIPS, codenamed LIGHTNING
• A600+ – enhanced with code/data separation and optional ECC memory
• Circa 1982 A700 – Am2903 bit-slice CPU with optional floating-point capability, running at 1 MIPS, codenamed PHOENIX
• 1984 A900 – featuring a pipelined data path, achieving 3 MIPS with ECC memory, codenamed MAGIC
• 1986 A400 – single-board CPU including serial lines, manufactured using CMOS-40 process technology, codenamed Yellowstone
• 1992 A990 – dual CMOS ASIC CPUs supporting up to 512 MB of RAM

HP minicomputers

Year	Model	Microword size	Microcode capacity	Microword types	ALU	Carry generator	Micro sequencer
1973	2100S	24	1K	3	4×74181	74182	Discrete
1974	1000 M-Series	24	4K	4	4×74181	74182	Discrete
1976	1000 E-Series	24	16K	4	4×74S181	74S182	Discrete
1978	1000 F-Series	24	16K	4	4×74S181	74S182	Discrete
?	F-Series FPP	?	?	?	4×74S181	74S182	Discrete
1980	1000 L-Series	?	?	?	Custom CMOS/SOS
1981	1000 A600	56	4K	5	4×2901B	74S182	2910+2904
1982	1000 A700	32	16K	11	4×2903	74S182	2911
1984	1000 A900	48	32K	4	4×74S381	74S182	Discrete
1986	1000 A400	32	16K	11	Custom CMOS/SOS

Legacy

The HP 2000 series, launched in 1969 and marketed until 1978 with ongoing support until 1985, played a significant role in early computing history.

This platform was home to several pioneering BASIC games, notably Mike Mayfield's influential Star Trek game from 1971. The widespread popularity of this title helped establish its BASIC dialect as a common standard, leading to many BASIC programs being published in this variant, including those by the People's Computer Company. HP systems were also extensively utilized in business education environments for instruction in statistics, regression analysis, and economics.

21st century

The designations HP 2000 and HP 2100 have been reassigned in modern contexts:

• The name HP 2000 currently refers to an entry-level laptop series.
• The term HP 2100 is now associated with a line of LaserJet printers.

Memory organization

During the era when the HP 2100 was developed, the price of magnetic core memory was rapidly declining, whereas implementing processor registers using transistors or small-scale integration remained relatively expensive. This economic factor led to architectures featuring a limited number of registers and relying heavily on RAM for storage, shaping the instruction set architecture (ISA) toward a memory-memory or memory-accumulator style, akin to the 12-bit PDP-8.

The system employs 15-bit addresses, allowing access to up to 32,768 16-bit words (64 KB). The smallest accessible unit is a full 16-bit word; no instructions exist for handling individual bytes. Addressing divides into a 5-bit page selector (out of 32 pages) and a 10-bit offset within that page. In the 21MX series' DMS system, the upper 5 bits select one of 32 registers (each with 12 bits), which combine with the offset to create a full 20-bit address. The two highest bits provide memory protection capabilities.

Processing centers on two primary 16-bit registers, A and B, which can also be referenced as memory locations 0 and 1. For instance, the instruction LDA 1 copies the content of register A into memory location 1, effectively transferring A’s value into B.

Additional CPU registers include M, holding the current memory address; T, containing the data at that address; and P, functioning as both the program counter and base for certain calculated memory accesses stored in M. Two single-bit flags, Overflow and Extend, serve as status indicators. Moreover, a 16-bit S/D (Switch/Display) register manages front panel input and output operations.

Specific memory regions are reserved: locations 0 and 1 house accumulators; the lowest 64 words support direct memory access (DMA) and vectored interrupts; and in later models, the highest 64 words contain the boot loader.

Instructions

HP 2116 registers

15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00	(bit position)
Accumulators
A
B
Program Counter
	P (page)					P (address)
Flags
														O	X

The initial instruction set comprised between 68 and 70 commands.

• Arithmetic operations: Add, Increment, And, Or, Exclusive Or
• Program flow control: Skip, Jump, Jump to Subroutine
• Bit manipulation: Arithmetic and Logical Shifts, Rotates of 16 and 17 bits
• Optional extensions: Multiply, Divide, Load/Store of 32-bit values, 32-bit Shifts

All standard instructions occupy 16 bits and most execute within a single memory cycle (equivalent to 16 clock cycles), although indirect addressing modes and the ISZ instruction may require up to 36 cycles. Conditional branching is implemented via a skip-one instruction followed by a jump. Subroutines do not utilize an internal stack; instead, the return address is stored at the subroutine's initial memory location using the JSB instruction. This approach necessitates programmer-managed stacks for reentrant code.

The ISA divides instructions into three categories: memory reference instructions, register reference instructions, and input/output instructions. Some variants expanded this set by adding floating-point or advanced mathematical commands within these groups.

Memory reference instructions allocate six bits for opcode and flags while reserving ten bits for addressing. The highest bit (bit 15) indicates indirect addressing mode, permitting multiple levels of pointer dereferencing until reaching a direct address. Bit 10 governs addressing mode: when cleared, it targets zero page addressing (the first 1,024 words); when set, it combines with the current page register to access one of thirty-two pages each containing 1,024 words. This scheme allows simultaneous addressing of up to 2,048 words—half in zero page and half within the current page.

Register reference instructions omit address fields entirely, freeing bits to encode multiple operations per word—up to four or eight instructions—thereby improving execution efficiency. There are thirty-nine register operations divided into shift-and-rotate and alter-and-skip groups. Bit 10 differentiates these groups; bit 11 selects between register A or B.

Shift-and-rotate instructions perform bit-level manipulations with up to four encoded per word; notably, the middle two are always CLE (clear E) and SLA/B (skip if zero). Alter-and-skip comprises eight instructions that increment registers and conditionally branch based on their results—commonly used for loop control mechanisms.

Input/Output and Interrupt Handling

Communication via Input/Output instructions occurs through the accumulators, employing an instruction format that begins with "1000" in the highest bits. This is followed by a bit indicating register choice (A=0, B=1), then a "1", the H/C flag bit, three bits specifying the instruction, and finally six bits designating the I/O device ID or channel, allowing support for up to 64 devices. Certain device IDs are reserved for system-specific functions.

To initiate I/O operations, the Flag bit is cleared using STF, and the C bit is set with STC. The hardware recognizes this signal pattern to commence processing. Once the operation finishes, the device sets the Flag bit, enabling data transfer through LI* or OT* instructions.

Data movement predominantly relies on the interrupt mechanism. Memory addresses 4 through 63 store pointers to interrupt service routines, providing 60 distinct interrupt levels. Locations 4 to 7 are designated for critical conditions such as power failures, parity errors, and memory protection faults; addresses from 8 onward serve as user-accessible vectors linked to I/O channels arranged by priority. For instance, if device number 13 triggers an interrupt, the CPU branches to memory address 13 unless preempted by higher-priority interrupts.

A distinctive aspect of the 2100 series is its dedicated direct memory access (DMA) controller that utilizes cycle stealing to access memory during CPU idle cycles. This approach permits extensive I/O operations to proceed simultaneously with CPU activities. The DMA controller (channel 6) is configured through I/O commands specifying parameters like device ID, transfer direction (input or output), starting memory address, and word count. Initialization routines frequently reside in interrupt vectors to automate DMA control. Separate mapping tables for CPU and DMA facilitate loading data into different extended memory segments.

Software Development

HP supplied a three-pass assembler featuring a column-separated syntax: labels begin in column one, followed by operation codes and operands; comments occupy the remainder of the line. This assembler accepts fundamental arithmetic expressions and includes pseudo-operations such as ORG for defining program load addresses.

The original software package encompassed the assembler, linker, FORTRAN 66 compiler, operating system, and device drivers. Subsequently, additional programming languages were introduced including BASIC, ALGOL, FORTRAN IV, and FORTRAN 77.

Enhancements to BASIC were made by porting AGL commands to support graphical output on terminals and plotters. A comparable graphics extension named GRAPHICS/1000 was offered for FORTRAN users.

Operating System Environments

The 2100 series commonly operated under the "Real Time Executive" (RTE) OS family, with multiple variants tailored for specific hardware: RTE-II targeted models 2114 through 2116; RTE-III was designed for standard 2100 systems; RTE-IV supported the 21MX line; and RTE-A catered to the "A" series machines.

The operating system provided a minimal shell environment featuring a single-level file system known as File Manager (FMGR). For example, invoking a FORTRAN compiler involved commands formatted as:

ru, f77, &test,'test,%test

which differentiated source code, object files, and executables using special delimiters.

File naming conventions on HP 1000 systems were restricted to five characters, complicating software development and portability efforts. Later versions like RTE-A introduced hierarchical directory structures supporting filenames up to sixteen characters with four-character extensions (16.4 format) and made usage of the ru command optional.

TODS (Test Oriented Disk System), created at HP’s board repair facility, enhanced diagnostic program loading by replacing paper tape media with centralized disk storage solutions. TODS found widespread application across HP 2116 through 21MX-F systems deployed in missile testing platforms such as Phoenix, Harpoon, Tomahawk, among others. Specialized test equipment including the 9500D-A46 Minuteman tester and ATS-E35 Peacekeeper/Minuteman launch component testers operated under TODS control. Additionally, HP’s microwave analyzers like the 8580/8542 ANA/ASA and TDRSS microwave transponder test sets utilized this system.

MTOS (Magnetic Tape Operating System) functioned as a related platform running alongside TODS in certain environments.

Descendants and Variants

The HP 9810, 9820, and 9830 desktop models incorporated a slower TTL variant of the 2116 processor; however, they did not utilize its original operating systems or software. These systems instead relied on ROM-based interpreters such as BASIC, and featured built-in keyboards and displays in place of disk drives or external terminals. In 1975, Hewlett-Packard launched the BPC (Binary Processing Chip), among the earliest 16-bit microprocessors, fabricated using HP’s NMOS-II technology. This chip was housed in ceramic hybrid modules alongside EMC and IOC chips, which extended mathematical and input/output instruction capabilities, powering the 9825 desktop computer. The subsequent 9845 workstation introduced a MMU, enhancing memory control. These devices served as forerunners to today’s personal computers and specialized technical workstations.

Significant architectural changes between the original 2116 CPU and the BPC included a revamped input/output framework, elimination of multiple levels of indirect addressing, and integration of a stack register to manage subroutine calls. These modifications facilitated an increase in addressable memory from 32K to 64K 16-bit words. Additionally, the BPC supported "current page" addressing relative to the instruction pointer rather than relying on fixed page boundaries.

The BPC found extensive application across HP computers, peripherals, and test instruments until it was phased out in the late 1980s.

In Poland, HP 2114B clones began production in 1973 with prototypes such as the MKJ-28, followed by pilot models like the SMC-3, and finally series production units named PRS-4, exceeding 150 machines.

Czechoslovakia engineered HP 1000-compatible clones under the ADT4000 lineup (spanning models 4300 to 4900). Development was led by Aritma Prague, with manufacturing by ZPA Čakovice and ZPA Trutnov. From 1973 through 1990, over a thousand units were delivered. These dependable real-time computers supported applications in power generation—including nuclear facilities—industrial sectors, military operations, and academic institutions. Their operating systems comprised DOS/ADT variants along with Unix implementations. Highlighted models include the ADT4316 equipped with 16K ferrite core memory; the ADT4500 featuring up to 4M semiconductor RAM; and the ADT4900 designed as a single-board computer that never reached mass production. The Czechoslovak People's Army deployed ADT-based MOMI mobile minicomputers mounted on Tatra trucks for field operations.

Bibliography

• The Hewlett Packard Company. HP1000/RTE Home page.

External links

• Jeff Moffat's HP2100 Archive: software and manuals
• Simulator with executable binaries and source in C
• 1972 HP 2100 Brochure
• Rack-mounted HP2100 system Image illustrating a 21MX E-series computer, 2100A computer, power supplies, disk drives, and tape devices.
• HP Computer Museum: 1000-L & A Series
• Computer History Museum: The HP Way, HP 2116, Year 1966.