IBM A2
| Company type | Open source processor core |
|---|---|
| Industry | Semiconductor, Microprocessor design |
| Founded | 2010 |
| Founder | IBM |
| Products | A2I, A2O cores; used in PowerEN and Blue Gene/Q processors |
| Parent | IBM |
The IBM A2 processor core is an open source multicore, multithreaded 64-bit implementation of the Power ISA architecture, developed by IBM in accordance with the Power ISA version 2.06 specification. Available models include a 16-core variant operating at 2.3 GHz with a power consumption of 65 W, as well as a four-core version running at 1.4 GHz drawing 20 W.
Design
The A2 core is intended for customization and embedded system-on-chip (SoC) applications, building upon IBM’s experience with game console CPUs such as the Xbox 360 and the Cell processor used in the PlayStation 3.
A2I
The A2I core supports four-way simultaneous multithreading and implements the 64-bit Power ISA v.2.06 Book III-E embedded platform specification, including features for embedded hypervisor support. Engineered for high throughput and numerous concurrent threads, it was developed using VHDL.
It offers 4 sets of 32 general-purpose 64-bit registers with comprehensive support for both little and big endian formats, along with 16 KB each of instruction and data caches. Branch prediction is handled by a fine-grained unit comprising eight branch history tables, each with 1024 entries. The L1 cache architecture consists of a 16 KB data cache that is 8-way set associative and a 16 KB instruction cache that is 4-way set associative. The pipeline operates in order, issuing two instructions per cycle: one directed to a six-stage ALU and another optionally routed to an auxiliary execution unit (AXU).
Although equipped with a memory management unit (MMU), the core does not include a floating point unit (FPU). Instead, the AXU manages floating point operations along with other specialized functions through support for standardized or custom macros such as FPUs, vector processing units, DSPs, and media accelerators beyond the Power ISA instruction set. The system interface unit facilitates communication with other on-chip cores via a 256-bit write data interface and a 128-bit read interface for instructions and data, both operating at full core frequency.
A2O
The A2O represents a more recent iteration implemented in Verilog, compliant with Power ISA v.2.07 Book III-E. It emphasizes enhanced single-thread performance and targets speeds up to 3 GHz using a 45 nm fabrication process. Compared to the A2I, the A2O supports two-way simultaneous multithreading, larger L1 caches of 32 KB each for instructions and data, and incorporates out-of-order execution capabilities.
To date, no commercial products have been released utilizing the A2O core.
OpenSource
In late 2020, IBM made both the A2I and A2O cores available under a Creative Commons license, releasing their source code written in VHDL and Verilog on GitHub. This initiative was intended to broaden the range of freely available processor cores within the OpenPOWER Foundation. However, since the A2 designs originated in 2010, neither A2I nor A2O fully comply with the mandatory Power ISA versions 3.0 or 3.1 required for OpenPOWER cores today. IBM advocates for community-driven updates to bring these cores into alignment with current ISA standards.
PowerEN
The PowerEN (Power Edge of Network), often referred to as the "wire-speed processor," combines traditional network processing functions such as switching and routing with server-class processing capabilities tailored for data manipulation tasks. Unveiled at ISSCC 2010, this chip integrates the A2I core alongside an 8 MB cache and dedicated accelerators optimized for XML, cryptography, data compression, and regular expression processing — each equipped with its own memory management unit (MMU). Connectivity features include four 10 Gigabit Ethernet interfaces and two PCIe lanes. The design supports scaling up to four chips in an SMP configuration without requiring additional support hardware. The complex chip comprises approximately 1.43 billion transistors on a die measuring 428 mm2, fabricated using a 45 nm process technology.
Blue Gene/Q
The Blue Gene/Q processor incorporates 18 cores based on the A2I architecture, operating at a frequency of 1.6 GHz and engineered to facilitate rapid thread context switching. It includes a quad SIMD floating-point unit, a five-dimensional torus network for chip-to-chip communication, and an external I/O bandwidth of 2 GB/s. These cores are linked through a crossbar switch functioning at half the core speed, which connects to a multi-versioned 32 MB eDRAM L2 cache designed to support speculative execution and transactional memory. Memory support is provided by dual DDR3 controllers running at 1.33 GHz, accommodating up to 16 GB of RAM.
Out of the total 18 cores, 16 are dedicated to computational workloads, one core is assigned to handle operating system services such as interrupts, asynchronous I/O, MPI flow control, and reliability, availability, and serviceability (RAS), while the remaining core acts as a redundant spare to replace any defective cores identified during manufacturing. Produced using IBM's 45 nm copper SOI fabrication process, this chip measures 19×19 mm (359.5 mm2) and contains approximately 1.47 billion transistors. It achieves a peak performance of up to 204.8 GFLOPS while consuming 55 watts of power.