IBM Power microprocessors

IBM POWER
Company type	Microprocessor architecture
Industry	Computer hardware
Founded	1990
Founder	IBM
Headquarters	Armonk, New York, United States
Products	POWER microprocessors, PowerPC processors, Power ISA
Website	https://www.ibm.com/it-infrastructure/power

Power microprocessors—known as POWER before the release of Power10—are designed and marketed by IBM primarily for use in servers and supercomputers. The acronym "POWER" represents "Performance Optimization With Enhanced RISC." This processor series has been the foundation for IBM's RS/6000, AS/400, pSeries, iSeries, System p, System i, and Power Systems lines of servers and supercomputers. Additionally, manufacturers such as Bull and Hitachi have integrated these processors into their servers, storage solutions, and workstations.

The Power architecture originated in the late 1980s with the introduction of the POWER ISA, which subsequently evolved into the PowerPC architecture and later the unified Power ISA. In August 2019, IBM made a significant move to open source the Power ISA, transferring governance of the OpenPOWER Foundation to the Linux Foundation.

The 801 initiative

In 1974, IBM launched a project aimed at creating a high-speed telephone switching computer. The design prioritized simple instructions—managing I/O operations, branching, register-to-register addition, and data transfers between registers and memory—while excluding complex arithmetic commands. This design philosophy ensured each instruction executed in a fixed time frame and later became recognized as RISC. Although the telephone switching project was ultimately discontinued, IBM preserved the design concept as a versatile processor called 801, developed at the Thomas J. Watson Research Center.

The Cheetah initiative

By 1982, IBM had refined the 801 design to investigate superscalar processing by employing multiple execution units to enhance throughput. The Cheetah processor included dedicated units for branch prediction, fixed-point arithmetic, and floating-point operations. By 1984, IBM adopted CMOS technology to improve transistor performance and circuit density.

The America initiative

In 1985, development began at IBM’s Thomas J. Watson Research Center on a second-generation RISC architecture named "AMERICA." By 1986, IBM’s Austin facility was producing RS/6000 computers based on this architecture, marking the debut of the first POWER processors implementing the POWER ISA.

POWER era

Introduced in February 1990, the RS/6000 series were IBM’s inaugural systems utilizing the POWER ISA. This lineup featured both POWERstation workstations and POWERserver servers. The original RS/6000 CPU was available in two variants: the 10-chip "RIOS-1" and a more cost-effective 8-chip version known as "RIOS.9" (often referred to as POWER1). The RIOS-1 architecture separated functions across chips dedicated to instruction cache, fixed-point operations, floating-point processing, multiple data caches, storage control, I/O handling, and clock management. The RIOS.9 model simplified this configuration by reducing cache chips and I/O components.

POWER1 was innovative as it introduced register renaming and out-of-order execution within a microprocessor for the first time. In 1992, a compact single-chip version named RISC Single Chip (RSC) was released targeting lower-end RS/6000 models.

POWER1 processor variants

RIOS-1 — original 10-chip configuration
RIOS.9 — streamlined version of RIOS-1
POWER1+ — upgraded RIOS-1 fabricated with smaller process technology
POWER1++ — further refined iteration of POWER1+
RSC — single-chip adaptation of RIOS-1
RAD6000 — radiation-hardened variant of RSC extensively utilized in space applications

POWER2

IBM introduced the POWER2 processor as the follow-up to POWER1, incorporating an additional fixed-point unit, a second floating-point unit, and new instructions to enhance overall performance. Unveiled in November 1993, it set a new benchmark for processing capabilities in the industry. The multi-chip POWER2 was also available in a single-chip format known as the POWER2 Super Chip (P2SC), which powered advanced servers and supercomputers. Released in 1996, the P2SC was notable for having the highest transistor count at the time and demonstrated exceptional floating-point performance.

POWER2 processors

POWER2 — consisted of 6 to 8 chips mounted on a ceramic multi-chip module
POWER2+ — a more cost-effective 6-chip variant supporting external L2 caches
P2SC — a single-chip, higher-speed version of the POWER2
P2SC+ — an enhanced P2SC featuring a smaller fabrication process

PowerPC

In 1991, Apple pursued an alternative to the Motorola 68000 CISC-based platform while Motorola was developing its own RISC architecture, the 88000. IBM collaborated with Apple and Motorola to establish the AIM alliance, resulting in the creation of the PowerPC instruction set architecture (ISA), which was derived from IBM’s POWER ISA with contributions from Apple and Motorola. This 32/64-bit RISC architecture was designed to serve a wide array of applications ranging from embedded controllers to high-performance servers and supercomputers.

After two years of development, PowerPC was launched in 1993, enhancing the RSC architecture by introducing single-precision floating-point instructions, register-to-register multiply/divide operations, a 64-bit mode, and support for symmetric multiprocessing (SMP).

The Amazon project

In 1990, IBM sought to consolidate its low-end RS/6000 RISC and midrange AS/400 CISC server platforms under a unified RISC ISA capable of running both AIX and OS/400 operating systems. Since neither POWER nor PowerPC ISAs were compatible with AS/400 requirements, IBM developed PowerPC AS (Advanced/Amazon Series), a 64-bit extension tailored for this purpose. By 2001, with the introduction of POWER4, these developments merged RS/6000 and AIM Alliance PowerPC features into a single PowerPC version 2.0 ISA.

POWER3

The POWER3 processor emerged as a hybrid solution combining elements from POWER2 and both 32- and 64-bit PowerPC ISAs following the limited success of the PowerPC 620. It supported symmetric multiprocessing (SMP) and was implemented as a single-chip design. Widely deployed within IBM’s RS/6000 systems, its successor—the POWER3-II—was IBM’s first chip to utilize copper interconnect technology. The POWER3 marked the final generation to use the original POWER instruction set; subsequent processors transitioned exclusively to PowerPC ISAs.

POWER3 processors

POWER3 – Released in 1998, integrating both POWER and PowerPC instruction sets
POWER3-II – An improved version of POWER3 manufactured using a smaller copper-based process

POWER4

The POWER4 processor combined the 32/64-bit PowerPC ISA with the Amazon project’s 64-bit PowerPC AS into a unified PowerPC version 2.0 ISA, effectively merging IBM’s RS/6000 and AS/400 server families. Engineered for high clock frequencies and substantial on-die L2 cache capacity, it represented IBM’s first commercially available multicore processor. Available as both a single-die chip and as part of four-chip multi-chip modules, it addressed diverse performance needs. In response to Apple’s request in 2002, IBM developed a cost-reduced variant known as the PowerPC 970.

POWER4 processors

POWER4 – Recognized as the first dual-core microprocessor and the initial PowerPC chip to surpass 1 GHz clock speed.
POWER4+ – An upgraded variant of the POWER4, manufactured using a smaller fabrication process for enhanced efficiency.

POWER5

Building upon the POWER4 architecture, the POWER5 processors introduced simultaneous multithreading and integrated memory controllers on the same die. Engineered for extensive multiprocessing environments, these chips utilized multi-chip modules incorporating large L3 caches.

POWER5 processors

POWER5 – A multi-chip module composed of four POWER5 cores alongside four L3 cache chips.
POWER5+ – A refined version produced with a reduced process technology to lower power usage.

Power ISA

In 2004, Power.org was founded to consolidate the diverse PowerPC standards that IBM and Freescale had developed independently. IBM concentrated on high-performance servers and supercomputers, whereas Freescale specialized in 32-bit embedded systems. Coordination was also necessary among licensees such as AMCC, Synopsys, Sony, Microsoft, P.A. Semi, CRAY, and Xilinx.

The unified instruction set architecture, Power ISA version 2.03, combined PowerPC v.2.02 from the POWER5 line with Freescale’s Book E specification and incorporated technologies like AltiVec (VMX) and hardware virtualization support. The POWER6 processor was the first high-end chip to implement this ISA, with earlier PowerPC instruction sets being phased out and no longer maintained.

POWER6

Developed under IBM’s eCLipz initiative to unify the I (AS/400), P (RS/6000), and Z (mainframe) instruction sets onto a single platform, POWER6 represented a significant step forward. While I and P were merged during the POWER4 generation, the CISC-based z/Architecture remained distinct and evolved separately in processors such as the IBM Telum.

The design focus of POWER6 shifted towards achieving extremely high clock rates rather than relying on out-of-order execution. It also introduced a decimal floating-point unit shared with z/Architecture processors.

In 2008, IBM merged its System p and System i server lines into the consolidated Power Systems family. These servers support multiple operating systems including AIX, Linux, and IBM i, offering greater versatility for enterprise applications.

POWER6 processors

POWER6 – Achieved clock speeds up to 5 GHz; available as both single-chip modules and multi-chip modules featuring two L3 cache chips.
POWER6+ – A modest revision fabricated using the same process technology as the original POWER6.

POWER7

The introduction of the POWER7 symmetric multiprocessing processor marked a notable advancement over its predecessor, emphasizing energy efficiency through multiple cores, simultaneous multithreading (SMT), out-of-order execution capabilities, and large on-die eDRAM L3 caches. This eight-core chip supports up to 32 concurrent threads and includes core disabling features to boost frequency on active cores. It debuted the VSX floating-point unit that merges traditional FPU operations with AltiVec functionality. Although its clock speeds are lower than those of POWER6, each individual POWER7 core delivers superior performance.

POWER7 processors

POWER7 – Offered as single-chip modules or quad-chip multi-chip modules tailored for supercomputing applications.
POWER7+ – Manufactured with a smaller fabrication node, featuring increased L3 cache size and higher operating frequencies.

POWER8

The POWER8 processor operates at 4 GHz and features 12 cores, each supporting 8 simultaneous hardware threads, culminating in a total of 96 concurrent threads. It includes 96 MB of embedded eDRAM L3 cache on the chip and an additional 128 MB L4 cache located off-chip. This generation introduced the CAPI (Coherent Accelerator Processor Interface) extension bus over PCIe, replacing the previous GX bus, which facilitates connection to dedicated external accelerators like GPUs, ASICs, and FPGAs. IBM asserts that POWER8 delivers performance improvements two to three times greater than its predecessor, POWER7. The initial manufacturing process for POWER8 utilized a 22 nm technology node in 2014. Support for POWER8 features was incorporated into the Linux kernel starting in 2012.

POWER9

Developed by IBM, POWER9 integrates features from Power ISA version 3.0, released in 2015, including VSX-3 instruction sets and compatibility with Nvidia's NVLink interconnect technology. Under a contract with the U.S. Department of Energy, IBM and Nvidia collaborated to create the Sierra and Summit supercomputers, which combine POWER9 CPUs with Nvidia Volta GPUs; Sierra debuted in 2017, followed by Summit in 2018.

POWER9 was introduced in 2017 using a 14 nm FinFET fabrication process and is available in four variants: two models with 24 cores supporting SMT4 aimed at PowerNV systems for both scale-up and scale-out applications, alongside two models featuring 12 cores with SMT8 tailored for PowerVM virtualization environments. The architecture is open-source under the OpenPOWER Foundation, enabling licensing and customization by third parties.

Power10

Released in September 2021, Power10 is built on a 7 nm process and represents the next evolution of IBM’s Power architecture.

Power11

Debuting in July 2025, Power11 continues IBM’s pursuit of high-performance processors designed to address AI workloads and enterprise computing demands.

Devices

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Name	Image	ISA	Bits	Cores	Fab	Transistors	Die size	L1	L2	L3	Clock	Package	Introduced
RIOS-1		POWER	32-bit	1	1.0 μm	6.9 million	1284 mm²	8 KB instruction 64 KB data	n/a	n/a	20–30 MHz	Ten chips in CPGA on PCB	1990
RIOS.9		POWER	32-bit	1	1.0 μm	6.9 million		8 KB instruction 32 KB data	n/a	n/a	20–30 MHz	Eight chips in CPGA on PCB	1990
POWER1+		POWER	32-bit	1		6.9 million		8 KB instruction 64 KB data	n/a	n/a	25–41.6 MHz	Eight chips in CPGA on PCB	1991
POWER1++		POWER	32-bit	1		6.9 million		8 KB instruction 64 KB data	n/a	n/a	25–62.5 MHz	Eight chips in CPGA on PCB	1992
RSC		POWER	32-bit	1	0.8 μm	1 million	226.5 mm²	Unified 8 KB cache	n/a	n/a	33–45 MHz	CPGA with 201 pins	1992
POWER2		POWER2	32-bit	1	0.72 μm	23 million	Die sizes:1042.5 mm²,819 mm²	32 KB instruction 128–265 KB data	n/a	n/a	Clock speeds from 55 to71.5 MHz	Multiple dies assembled on ceramic MCMs (6–8)	Released between1993 and1994
Name	Image	ISA	Bits	Cores	Fab	Transistors	Die size	L1	L2	L3	Clock	Package	Introduced

External links

IBM Announces $1 Billion Linux Investment for Power Systems