POWER7
| Company type | Microprocessor series |
|---|---|
| Industry | Semiconductors |
| Predecessor | POWER6, POWER6+ |
| Founded | 2010 |
| Headquarters | Rochester, MN; Austin, TX; Essex Junction, VT; Yorktown Heights, NY; Bromont, QC; Böblingen, Germany , United States, Canada, Germany |
| Products | POWER7 microprocessors |
| Parent | IBM |
POWER7 represents a series of superscalar multi-core microprocessors built on the Power ISA 2.06 instruction set architecture. Introduced in 2010 as the successor to the POWER6 and POWER6+, it was developed by IBM across several locations including Rochester, MN; Austin, TX; Essex Junction, VT; the T. J. Watson Research Center in NY; Bromont, QC; and Böblingen, Germany. POWER7 signified a major technological leap for IBM’s processor portfolio. On 8 February 2010, IBM unveiled servers powered by POWER7 aimed at handling data-heavy enterprise applications.
History
In November 2006, IBM secured a $244 million contract from DARPA to create a petascale supercomputer architecture by 2010 as part of the HPCS initiative. A key requirement was that the architecture be commercially available upon completion. IBM’s successful proposal, named PERCS (Productive, Easy-to-use, Reliable Computer System), integrated the POWER7 processor with the AIX operating system and the General Parallel File System.
Collaboration between IBM and DARPA led to enhancements in addressing and page table hardware tailored for POWER7 clusters. This enabled a globally shared memory model, allowing programmers to treat clusters as unified systems without relying on message passing. The approach improved productivity for users less experienced with MPI or parallel programming techniques.
Design
The POWER7 architecture advances beyond POWER6 by focusing on power efficiency through multiple cores and simultaneous multithreading (SMT). Whereas POWER6 emphasized high clock speeds with a dual-core design operating at 5 GHz, POWER7 offers configurations up to eight cores per chip, each supporting four threads simultaneously, amounting to 32 concurrent threads.
At ISCA 29, IBM highlighted that earlier designs achieved peak performance via high-frequency pipelines characterized by 10–20 FO4 delays per stage but at the expense of power efficiency. The floating-point pipeline of POWER6 was optimized to "6-cycle, 13-FO4" delays. For POWER7, CPU pipeline design reverted to strategies similar to those used in POWER5 and POWER6, aligning with Intel’s mid-2000s shift away from ultra-high-frequency microarchitectures.
Specifications
POWER7 chips are available with 4, 6, or 8 physical cores and support configurations up to 32-way multiprocessing with a total of 1024 simultaneous multithreading (SMT) threads. In high-performance computing systems such as the Power 775, it is packaged as a quad-chip module (QCM) containing four processors for a combined total of 256 cores and 1024 SMT threads. The TurboCore mode uniquely disables half of the cores on an eight-core chip to increase clock speeds and memory bandwidth on the remaining cores. This mode enhances sequential processing performance while reducing licensing fees for software priced per core. IBM Power 780 servers utilize TurboCore to achieve up to twice the per-core throughput compared to POWER6-based systems.
Each core supports four-way SMT execution. The POWER7 processor integrates roughly 1.2 billion transistors on a 567 mm2 die using a 45 nm SOI fabrication process. Unlike the in-order execution model of POWER6, POWER7 cores execute instructions out-of-order, which improves efficiency despite a lower maximum clock frequency (4.25 GHz compared to POWER6's 5 GHz). This generation offers up to four times more cores than its predecessor.
Notable specifications include:
- Fabricated on a 45 nm SOI process with a die size of 567 mm2
- Approximately 1.2 billion transistors
- Operating frequencies ranging from 3.0 GHz up to 4.25 GHz
- Up to four processors per quad-chip module
- Available with 4, 6, or 8 C1 cores per chip
- Each core supports four simultaneous SMT threads (compatible with AIX 6.1 TL05+)
- Twelve execution units per core:
- Two fixed-point units
- Two load/store units
- Four double-precision floating-point units
- One vector unit featuring VSX support
- One decimal floating-point unit
- One branch unit
- One condition register unit
- Cache structure per core:
- Separate L1 caches: 32 KB instruction and 32 KB data
- L2 cache of 256 KB
- Shared L3 cache up to 4 MB implemented using embedded DRAM (eDRAM), scalable up to 32 MB
The out-of-order execution engine can dispatch as many as six instructions per cycle and issue up to eight instructions simultaneously to execution units, maximizing throughput.
For an eight-core processor running at approximately 4.14 GHz, theoretical maximum single-precision (SP) floating-point performance is:
- Up to 99.36 GFLOPS per core
- Up to 794.88 GFLOPS per chip
Each core contains four SIMD units operating on 64-bit data and one SIMD VMX unit with a width of 128 bits capable of twelve multiply-add operations per cycle, delivering high SP throughput; double-precision (DP) performance is roughly half that level.
Comparatively, Intel’s Haswell CPUs introduced in 2013 deliver similar floating-point performance per core but differ architecturally and target distinct workload profiles. Benchmarking reveals that SPEC CPU2006 single-threaded floating-point results are comparable between POWER7 and Intel i7-4770 processors; however, performance varies widely depending on application type.
In summary, POWER7 offers competitive floating-point capabilities aligned with contemporary Intel designs while emphasizing scalability and optimization for enterprise-class and HPC workloads.
POWER7+
At the Hot Chips 24 conference held in August 2012, IBM unveiled the POWER7+ processor. This enhanced iteration delivers faster clock speeds, expanded cache capacity, and built-in accelerators, all fabricated using a 32 nm manufacturing technology.
The initial deployment of POWER7+ processors appeared in IBM Power 770 and 780 server models. These CPUs provide up to 80 MB of L3 cache (equivalent to 10 MB per core), support clock frequencies reaching 4.4 GHz, and enable up to 20 LPARs per individual core.
Products
By October 2011, IBM's lineup based on the POWER7 architecture encompassed the IBM Power Systems "Express" series (models 710, 720, 730, 740, 750), Enterprise class servers (770, 780, 795), and High Performance Computing variants (755, 775). The Enterprise category includes Capacity on Demand features. A summary of key technical specifications is provided below.
| Model | Socket Count | Core Count | CPU Frequency |
|---|---|---|---|
| 710 Express | 1 | 6 | 4.2 GHz |
| 710 Express | 1 | 8 | 4.2 GHz |
| 720 Express (8202-E4B, POWER7) | 1 | 8 | 3.0 GHz |
| 720 Express (8202-E4D, POWER7+) | 1 | 8 | 3.6 GHz |
| 730 Express | 2 | 12 | 4.2 GHz |
| 730 Express | 2 | 16 | 3.6 or 4.2 GHz |
| 740 Express | 2 | 12 | 4.2 GHz |
| 740 Express | 2 | 16 | 3.6 or 4.2 GHz |
| 750 Express | 4 | 24 | 3.72 GHz |
| 750 Express | 4 | 32 | 3.22 or 3.61 GHz |
| 755 | 4 | 32 | 3.61 GHz |
| 770 | 8 | 48 | 3.7 GHz |
| 770 | 8 | 64 | 3.3 GHz |
| 775 (Per Node) | 32 | 256 | 3.83 GHz |
| 780 (MaxCore mode) | 8 | 64 | 3.92 GHz |
| 780 (TurboCore mode) | 8 | 32 | 4.14 GHz |
| 780 (4 Socket Node) | 16 | 96 | 3.44 GHz |
| 795 | 32 | 192 | 3.72 GHz |
| 795 (MaxCore mode) | 32 | 256 | 4.0 GHz |
| 795 (TurboCore mode) | 32 | 128 | 4.25 GHz |
IBM also provides a selection of five POWER7-based blade servers within the IBM BladeCenter product family:
| Model | Core Count | CPU Frequency | Required Blade Slots |
|---|---|---|---|
| BladeCenter PS700 | 4 | 3.0 GHz | 1 |
| BladeCenter PS701 | 8 | 3.0 GHz | 1 |
| BladeCenter PS702 | 16 | 3.0 GHz | 2 |
| BladeCenter PS703 | 16 | 2.4 GHz | 1 |
| BladeCenter PS704 | 32 | 2.4 GHz | 2 |
Significant supercomputing initiatives that incorporate the POWER7 processor include PERCS and Watson.
See also
External links
- IBM POWER7 Systems – Official IBM POWER7 product information
- IBM POWER7 Technology and Systems – IBM Journal of Research and Development via IEEE Xplore
- IBM Secures DARPA HPCS Phase-III
- IBM Secures DARPA HPCS Phase-II
- IBM Achieves PERCS Milestone
- POWER780 SPECint_rate_base2006 Benchmark Results
- Technical Overview: IBM BladeCenter PS703 and PS704