IBM RS64
| Company type | Microprocessor series |
|---|---|
| Industry | Semiconductor |
| Founded | 1995 |
| Headquarters | Armonk, New York , United States |
| Products | RS64 microprocessors |
| Parent | IBM |
The IBM RS64 series of microprocessors, launched by IBM during the mid-1990s, served as the core processors for the RS/6000 and AS/400 server product lines.
These CPUs utilize the "Amazon" or "PowerPC-AS" instruction set architecture (ISA), which is an enhanced version of the PowerPC instruction set incorporating features from both POWER2 and the original AS/400 processor. Built with 64-bit architecture from the beginning, RS64 processors are tailored for commercial applications—focusing on superior integer performance, sizable caches, and frequent branch handling—while placing less priority on floating point operations compared to IBM’s POWER processor lineup.
Following the introduction of the POWER4, which merged the RS64 and POWER designs, the RS64 family was gradually retired.
History
The AS/400 development team at IBM Rochester initiated work on C-RISC (Commercial RISC) in 1990 to succeed the IMPI architecture. This project extended IMPI by increasing address space to 96 bits and adding RISC instructions optimized for AS/400 commercial workloads. Although IBM president Jack Kuehler supported adopting PowerPC, the team contended that existing 32- and 64-bit PowerPC ISAs lacked certain extensions necessary to support OS/400 software. As a result, under the leadership of Frank Soltis, the Rochester group explored augmenting PowerPC to fulfill AS/400 requirements, leading to the creation of the Amazon ISA enhancements. IBM management ultimately chose Amazon over C-RISC for further advancement.
At the same time, RS/6000 engineers broadened their offerings from entry-level workstations to high-end SMP enterprise systems and clustered supercomputers. While PowerPC processors developed by the AIM alliance were suitable for low-end workstations and small servers, more powerful systems required additional capabilities not found in Apple Power Mac–focused chips. This necessitated multiple processor designs to address Apple’s cost-sensitive market segment, high-performance RS/6000 machines, and AS/400’s migration to PowerPC.
Correspondingly, Amazon was expanded to accommodate these demands, enabling processors appropriate for both premium RS/6000 and AS/400 platforms.
The initial endeavor, called "Bellatrix" after a star in Orion, targeted advanced self-timed and pulse-based circuitry but was ultimately discontinued due to its complexity. To serve workstation, supercomputer, and engineering markets, IBM Austin developed a single-chip Power2 variant (P2SC) alongside an advanced 64-bit PowerPC processor featuring POWER2 extensions and dual MAF floating-point units (POWER3/630). Concurrently, IBM Rochester concentrated on high-end 64-bit PowerPC processors with AS/400-specific extensions for commercial use, while IBM Endicott produced low-end single-chip PowerPC processors incorporating similar enhancements.
Cobra and Muskie
IBM introduced the Cobra (A10) processor in 1995 as the first complete implementation of PowerPC AS tailored for IBM AS/400 platforms. This single-chip CPU operated between 50 and 77 MHz and was designed using a semi-custom methodology to meet aggressive time-to-market targets. It contained 4.7 million transistors on a die measuring 14.6 mm square (213 mm2) fabricated with IBM's CMOS 5L 0.5 μm process technology. Running at 3.0 V, it consumed up to 17.7 W at its peak frequency of 77 MHz and was packaged in a 625-contact ceramic ball grid array (CBGA) with dimensions of 32 mm square.
Prior to Cobra, IBM released a simplified version known as Cobra-Lite in 1994 for early IBM Advanced/36 systems. This variant excluded 17 PowerPC AS instructions that were not required for that platform.
In 1996, IBM rolled out Muskie (also referred to as A25 or A30), a high-performance multi-chip processor supporting 4-way SMP configurations for AS/400 servers. It operated at clock speeds ranging from 125 to 154 MHz and was manufactured using a BiCMOS fabrication process.
Both Cobra and Muskie processors were exclusively deployed within AS/400 and Advanced/36 systems.
RS64
Launched in 1997, the RS64 (also known as Apache) was developed as an evolution of the Cobra and Muskie processors, incorporating a more comprehensive PowerPC instruction set architecture. It was designed to serve both RS/6000 and AS/400 platforms. The chip included a total of 128 KB of on-chip L1 cache, paired with a 4 MB full-speed off-chip L2 cache connected via a 128-bit bus, and operated at clock speeds of 125 MHz. The RS64 supported symmetric multiprocessing (SMP) configurations with scalability up to 12 processors in IBM server systems.
Within AS/400 environments, it was identified as A35 and was previously referred to as the PowerPC 625. Positioned between the discontinued PowerPC 620 and the PowerPC 630 (which later evolved into POWER3), the RS64 was manufactured utilizing a BiCMOS fabrication process.
RS64-II
Introduced in 1998, the RS64-II (code-named Northstar) operated initially at 262 MHz and featured an 8 MB full-speed L2 cache on a 256-bit bus shared with the PowerPC 620 and POWER3 processors. This design enabled processor boards containing four RS64-II chips to be interchanged with similar four-way RS64 boards, allowing system upgrades without extensive hardware modifications. The RS64-II housed 12.5 million transistors on a die measuring 162 mm², consumed up to 27 watts of power, and was fabricated using a 0.35 μm CMOS technology.
Significantly, the RS64-II was the first widely marketed processor to support multithreading, maintaining execution context for two threads simultaneously and appearing as two logical processors to the operating system. IBM referred to this approach as "coarse-grained multithreading," where thread switching predominantly occurs during high-latency operations such as L2 cache misses, thereby enhancing performance for its in-order execution design.
In AS/400 systems, this processor was labeled as A50.
RS64-III
The RS64-III, or Pulsar, debuted in 1999 running at 450 MHz. It offered expanded 128 KiB L1 caches for both instructions and data, improved branch prediction accuracy, and reduced branch misprediction penalties to either zero or one cycle. Featuring a five-stage pipeline, it utilized a 256-bit wide L2 cache bus delivering bandwidth up to 14.4 GB/s from an 8 MiB L2 cache constructed with 225 MHz DDR SRAM.
Containing 34 million transistors on a 140 mm² die, the RS64-III was produced using a 0.22 μm CMOS process (7S) that incorporated six layers of copper interconnect.
In 2000, IBM introduced the IStar, an enhanced version of the RS64-III fabricated with a SOI process and copper interconnect technology, which increased its clock speed to 600 MHz. Architecturally identical to Pulsar, IStar represented IBM’s initial use of this advanced manufacturing method.
RS64-IV
Released in 2000, the RS64-IV (nicknamed Sstar) initially ran at 600 MHz before later models reached speeds of up to 750 MHz. It supported up to a 16 MB DDR L2 cache delivering bandwidth of 19.2 GB/s. The processor contained 44 million transistors on a die measuring 128 mm² and was fabricated using a 0.18 μm process technology. Unlike its POWER processor counterparts, the RS64-IV maintained low power consumption—under 15 watts per core.
During a time when POWER processors were trailing competitors in terms of clock frequency, the RS64 series dominated IBM’s large SMP UNIX server market segment. Its performance in integer and commercial workloads matched that of contemporary offerings from Sun Microsystems, though its floating-point performance was comparatively weaker than that of the POWER3-II, which remained significant throughout its operational period.
Additional resources
- Gwennap, Linley (31 July 1995). "IBM Develops PowerPC Chips for AS/400". Microprocessor Report.