POWER3
| Company type | Microprocessor |
|---|---|
| Industry | Computer hardware |
| Founded | October 5, 1998 |
| Headquarters | United States |
| Products | Microprocessors |
The POWER3 is a microprocessor developed and solely produced by IBM, implementing the 64-bit iteration of the PowerPC instruction set architecture (ISA). It incorporates all optional ISA instructions available at the time, including those inherited from the POWER2 POWER ISA that were absent in earlier PowerPC models. Launched on 5 October 1998, its first application was in the RS/6000 43P Model 260, a workstation designed for high-end graphics tasks. Originally planned to be named the PowerPC 630, the processor was renamed, likely to clearly differentiate server-focused POWER processors from the consumer-targeted 32-bit PowerPC variants. The POWER3 marked the successor to the P2SC variant of POWER2, finalizing IBM’s postponed migration from POWER to PowerPC architectures, which had been initially aimed for completion by 1995.
Operating at a clock speed of 200 MHz within IBM’s RS/6000 servers and workstations, the POWER3 also served as the core processor for the ASCI White supercomputer, which held the top position on the TOP500 list. This system utilized a dedicated "Nighthawk" chipset alongside an SP network. The POWER3 competed directly with contemporaries such as Digital Equipment Corporation's (DEC) Alpha 21264 and Hewlett-Packard's (HP) PA-8500 processors.
Description
Building upon the foundation of the earlier PowerPC 620—a late entrant that underperformed commercially and failed to gain traction—the POWER3 introduced several enhancements. It featured three fixed-point units and replaced the single floating-point unit (FPU) with two floating-point fused multiply–add units. Additionally, it incorporated a second load-store unit to boost floating-point throughput. Designed as a superscalar processor capable of out-of-order execution, it employed pipelines consisting of seven stages for integer operations, eight for load/store tasks, and ten for floating-point calculations.
The instruction fetch stage retrieves eight instructions per cycle from a 32 KB instruction cache into a buffer holding twelve entries. These are then decoded and up to four instructions can be issued each cycle into respective instruction queues. The issue bandwidth is constrained by queue capacities: one integer queue accepts a single instruction, another can handle up to four instructions simultaneously, as does the floating-point queue. This architecture results in a brief branch misprediction penalty of only three cycles.
During stage three, operands are read from duplicated general-purpose register files totaling 48 registers—comprising 32 general-purpose plus 16 rename registers—which support three integer units and two load/store units without incurring additional synchronization delays due to elevated clock frequencies. The floating-point register file contains 56 registers (32 floating-point plus 24 rename), allowing for increased out-of-order execution capabilities compared to the PowerPC 620.
Execution begins at stage four with up to eight instructions dispatched per cycle. Fixed-point operations are handled by three integer units: two identical units process most instructions with a one-cycle latency, while the third is dedicated to multiply and divide operations that have longer latencies—nine cycles for 64-bit multiplication and thirty-seven cycles for division. Two FPUs execute fused multiply-add instructions with a latency of four cycles; divide and square-root instructions require more cycles but benefit from specialized hardware accelerators (fourteen cycles for single-precision divide or square-root; up to twenty-two cycles for double-precision).
Instructions complete their execution phase in stage five for integer operations or stage eight for floating-point operations. They commit in stage six or nine respectively, followed by writeback after commitment. The POWER3 supports retiring up to four instructions every cycle.
The data cache was specifically optimized for scientific and technical computing workloads: its capacity was doubled to 64 KB; it became dual-ported through eight interleaved banks enabling two simultaneous loads or stores per cycle; and its cache line size was increased to 128 bytes. To preserve a four-cycle latency despite larger cache lines, the L2 cache bus width was expanded to 256 bits.
Fabricated using IBM’s CMOS-6S2 process—a hybrid technology combining 0.25 μm features with metal layers at 0.35 μm—the POWER3 chip integrated approximately 15 million transistors on a die measuring 270 mm2. It utilized five layers of aluminum interconnects and was housed in a ceramic column grid array package with 1,088 columns, resembling that of the P2SC but featuring a distinct pin configuration.
POWER3-II
The POWER3-II represented an improved iteration of the original POWER3, featuring an increased clock frequency of 450 MHz. This processor contained 23 million transistors packed into a 170 mm2 silicon die, manufactured using IBM's CMOS7S 0.22 μm technology with six layers of copper interconnect. In 2001, the POWER3-II was replaced by the POWER4 processor.
See also
References
- - details on POWER1, POWER2, and POWER3