Multimedia Acceleration eXtensions
| Company type | Instruction set extension |
|---|---|
| Industry | Computer architecture |
| Founded | 1990s |
| Founder | Hewlett-Packard |
| Products | MAX-1, MAX-2 instruction set extensions |
| Parent | Hewlett-Packard |
The Multimedia Acceleration eXtensions (MAX) represent a set of instruction set enhancements for the Hewlett-Packard PA-RISC instruction set architecture (ISA), created during the 1990s to boost the efficiency of multimedia applications.
MAX instructions manipulate 32- or 64-bit SIMD data types that hold multiple 16-bit integers inside general purpose registers. Their capabilities include performing additions, subtractions, and bit shifts.
The initial iteration, MAX-1, was developed for the 32-bit PA-RISC 1.1 ISA, whereas MAX-2 was tailored to the 64-bit PA-RISC 2.0 ISA.
Notability
Compared to other multimedia-focused CPUs, MAX stands out due to its more compact and versatile instruction set. This streamlined design lowers ongoing electronic expenses and simplifies architecture complexity, thereby improving overall cost-effectiveness. The instruction set demands only minor modifications to a CPU’s arithmetic-logic unit, serving as a prototype for multimedia instruction integration in other processors. The CPU already incorporated robust shift and bit-manipulation instructions such as "shift pair," "extract," "deposit," alongside standard bitwise logical operations.
In 1996, the introduction of the 64-bit "MAX-2" facilitated real-time decoding of MPEG-1 and MPEG-2 video formats, while increasing the RISC CPU chip area by a mere 0.2%, highlighting its efficiency gains.
Implementations
The debut of MAX-1 occurred with the PA-7100LC processor in 1994 and is frequently recognized as the first SIMD extension integrated into an ISA. MAX-2 followed with the launch of the PA-8000 microprocessor in 1996.
MAX-2 employs an arithmetic technique that "interrupts carries" between 16-bit subwords, enabling modular arithmetic as well as signed and unsigned saturation with minimal alterations to the arithmetic logic unit.
MAX-1
| Instruction | Description |
|---|---|
| HADD | Parallel addition using modulo arithmetic |
| HADD,ss | Parallel addition with signed saturation |
| HADD,us | Parallel addition with unsigned saturation |
| HSUB | Parallel subtraction using modulo arithmetic |
| HSUB,ss | Parallel subtraction with signed saturation |
| HSUB,us | Parallel subtraction with unsigned saturation |
| HAVE | Parallel averaging operation |
| HSHLADD | Parallel shift left followed by addition with signed saturation |
| HSHRADD | Parallel shift right followed by addition with signed saturation |
MAX-2
MAX-2 instructions perform register-to-register operations on multiple integers packed into 64-bit registers, all executing within a single cycle on the PA-8000 and its successors. Memory interactions utilize conventional 64-bit load and store instructions.
The introduction of "MIX" and "PERMH" instructions allows reordering of words inside registers without accessing memory, greatly enhancing processing speed.
| Instruction | Description |
|---|---|
| HADD | Parallel addition using modulo arithmetic |
| HADD,ss | Parallel addition with signed saturation |
| HADD,us | Parallel addition with unsigned saturation |
| HSUB | Parallel subtraction using modulo arithmetic |
| HSUB,ss | Parallel subtraction with signed saturation |
| HSUB,us | Parallel subtraction with unsigned saturation |
| HSHLADD | Parallel shift left then add with signed saturation |
| HSHRADD | Parallel shift right then add with signed saturation |
| HAVG | Parallel averaging operation |
| HSHR | Signed parallel shift right |
| HSHR,u | Unsigned parallel shift right |
| HSHL | Parallel shift left |
| MIX | Rearranges 16-bit subwords within a 64-bit register; e.g., MIX Left: Rc:=a1,b1,a3,b3; MIX Right: Rc:=a2,b2,a4,b4 |
| MIXW | Rearranges 32-bit subwords within a 64-bit register; e.g., MIXW Left: Rc:=a1,a2,b1,b2; MIXW Right: Rc:=a3,a4,b3,b4 |
| PERMH | Permutes 16-bit subwords in any sequence within the destination register, including duplicates. |