PA-7100LC
| Industry | Computer hardware |
|---|---|
| Founded | January 1, 1939 |
| Products | Microprocessors, computers, printers |
The PA-7100LC is a microprocessor that implements the PA-RISC 1.1 instruction set architecture (ISA) created by Hewlett-Packard (HP). Also referred to as the PCX-L and internally known as Hummingbird, it was engineered to serve as an economical option for entry-level systems. Systems utilizing the PA-7100LC debuted in January 1994, operating at clock speeds of 60 and 80 MHz, with a 100 MHz variant becoming available in June 1994. This processor was the first PA-RISC model to incorporate the MAX-1 multimedia instructions, an early form of single instruction, multiple data technology designed to improve MPEG video decoding efficiency.
Building upon the foundation of the PA-7100, the PA-7100LC introduced several important enhancements such as advanced superscalar capabilities through an additional integer execution unit and architectural improvements like MAX-1 multimedia instructions, support for uncacheable memory pages, and bi-endian functionality. The superscalar design allowed the processor to issue two integer instructions, two load–store unit operations, or a mix of integer and load/store instructions per cycle, thereby extending the execution abilities beyond those of its predecessor.
In terms of circuitry, modifications included a revamped floating-point unit multiplier which reduced chip size by halving the carry-save adder tree used for mantissa partial product calculations. While this maintained a two-cycle latency for single-precision multiplication, it increased double-precision latency to three cycles—a compromise deemed acceptable given the processor’s target market of mid-range multimedia workstations that primarily utilized single precision. Additionally, an integrated on-chip memory controller supported up to 2 GB of RAM, complemented by an I/O controller aimed at lowering overall system expenses.
The cache design diverged from other HP PA-RISC processors by substituting large external instruction and data caches with a modest 1 KB on-die instruction cache paired with a unified external cache ranging between 8 KB and 2 MB for both instructions and data.
Comprising approximately 900,000 transistors within a die measuring 14.2 by 14.2 mm (201.64 mm2), the PA-7100LC was manufactured using HP’s 0.8 μm three-level metal CMOS26B fabrication process. It was packaged in a 432-pin ceramic pin grid array.
PA-7300LC
Released in mid-1996, the PA-7300LC represented an advancement over the PA-7100LC and was positioned as a low- to mid-tier complement to the high-performance PA-8000 within HP’s lineup of workstations and servers. This processor integrated an improved PA-7100LC core along with 64 KB instruction and data caches, an L2 cache controller, memory controller, and a GSC bus controller all on a single die. It was notable for being the first PA-RISC CPU to incorporate substantial on-chip cache memory. The optional L2 unified cache supported parity error detection and could be implemented using register-to-register, flow-through, or asynchronous SRAM technologies.
Containing 9.2 million transistors—of which roughly 1.2 million were dedicated to logic circuits and 8 million to cache memory—the chip measured 15.3 by 17.0 mm (260.1 mm2) and was produced with HP’s CMOS14C process, a four-layer-metal CMOS technology operating at 0.5 μm feature size and 3.3 V.
A distinctive feature of this design is a "silicon doodle" depicting a velociraptor dinosaur located in the upper right corner of the die.
External links
Presentation on Hummingbird: An Affordable Superscalar PA_RISC Processor by Stephen Undy