PA-RISC

Hewlett-Packard

Industry	Computer hardware
Founded	January 1, 1939 (1939-01-01)
Headquarters	Palo Alto, California , United States
Products	PA-RISC architecture, HP 3000 Series, HP 9000 Series

Precision Architecture RISC (PA-RISC), also known as Hewlett Packard Precision Architecture (HP/PA or HPPA), represents a general-purpose computer instruction set architecture created by Hewlett-Packard throughout the 1980s and into the early 2000s.

Unveiled on 26 February 1986 alongside the debut of the HP 3000 Series 930 and HP 9000 Model 840, which incorporated the initial TS1 implementation, PA-RISC became the foundation for HP's enterprise-level computing platforms. While HP ceased sales of PA-RISC-based HP 9000 systems in 2008, support for these servers continued until 2013. This architecture was eventually replaced by the Itanium instruction set, a collaborative development between HP and Intel, signaling a strategic transition to advanced processor technologies.

History

During the late 1980s, Hewlett-Packard produced four distinct computer lines utilizing CISC processors. These included the Intel i286-powered Vectra Series launched in 1986, alongside non-Intel platforms such as the HP Series 300 workstations built on Motorola 68000 CPUs, Series 200 technical workstations featuring custom silicon on sapphire (SOS) chips, the SOS-based 16-bit HP 3000 classic lineup, and the HP 9000 Series 500 minicomputers with proprietary FOCUS microprocessors.

The Precision Architecture emerged from HP’s Spectrum initiative, which sought to consolidate their diverse non-PC compatible hardware under a unified RISC CPU family. Initiation of development took place in early 1982 at HP Laboratories, focusing on defining both the instruction set and virtual memory architecture. The first TTL prototype was constructed in April 1983, with finalized processor designs delivered to engineers by July 1984. Subsequent prototypes appeared throughout 1985 and 1986.

The inaugural products utilizing these processors were released in 1986, including the HP 9000 Series 840 models. Additionally, this architecture powered late-1980s HP 3000 Series 930 and 950 machines—known as "Spectrum" systems—running MPE-XL, whereas PA-RISC-based HP 9000 models operated with HP-UX. The original TS1 CPU was implemented using discrete TTL components; later iterations such as NS1, NS2, CS1, and PCX transitioned to multi-chip VLSI designs fabricated through NMOS and CMOS processes introduced by late 1987.

PA-RISC architecture is characterized by thirty-two 32-bit integer registers and sixteen floating-point registers initially sized at 64 bits but later expanded to thirty-two. It employs a single branch delay slot and incorporates a Processor Status Word (PSW) register that governs virtual addressing, protection mechanisms, and interrupt handling. Among its principal architects were Allen Baum, Hans Jeans, Michael J. Mahon, Ruby Bei-Loh Lee, Russel Kao, Steve Muchnick, Terrence C. Miller, David Fotland, and William S. Worley.

Various operating systems have been ported to PA-RISC platforms including Linux, OpenBSD, NetBSD, OSF/1, NeXTSTEP, and ChorusOS. Most PA-RISC processors across generations did not feature level 2 caches; instead, they relied heavily on substantial level 1 caches—initially implemented as separate chips before being integrated on-chip in later models. Exceptions include the PA-7100LC and PA-7300LC processors which incorporated L2 caches. The architecture introduced vector processing capabilities via Multimedia Acceleration eXtensions (MAX), implementing SIMD instructions first seen on the PA-7100LC.

In 1992, Hewlett-Packard spearheaded the creation of the Precision RISC Organization, an industry consortium established to promote PA-RISC technology. Its membership comprised companies such as Convex Computer, Hitachi, Hughes Aircraft, Mitsubishi, NEC, OKI, Prime, Stratus, Yokogawa, Red Brick Software, and Allegro Consultants, Inc..

The instruction set architecture was extended to support 64-bit computing in 1996 under PA-RISC version 2.0. This update introduced fused multiply–add operations enhancing floating-point processing efficiency along with MAX-2 SIMD extensions designed for multimedia acceleration. The first processor to implement PA-RISC 2.0 was the PA-8000, launched in January of that year.

CPU specifications

Image	Model	Marketing name	Year	Clock Speed [MHz]	Memory Bandwidth [MB/s]	Manufacturing Process [μm]	Transistor Count [millions]	Die Dimensions [mm2]	Power Consumption [W]	Data Cache [KB]	Instruction Cache [KB]	L2 Cache [MB]	ISA Version	Remarks
	TS-1	?	1986	8	?	?	—	—	?	64	64	—	1.0
	CS-1	?	1987	8	?	1.6	0.164	72.93	1	—	0.25	—	1.0
	NS-1	?	1987	25/30	?	1.7	0.144	70.56	?	16-128	16-128	—	1.0
	NS-2	?	1989	25/30	?	1.5	0.183	196	27	512	512	—	1.0
	PCX	?	1990	50/60	?	1.0	0.196	?	?	?	?	?	1.0
	PCX-S	PA-7000	1991	66	?	1.0	0.58	201.6	?	256	256	—	1.1a
	PCX-T	PA-7100	1992	33–100	?	0.8	0.85	196	?	2048	1024	—	1.1b
	PCX-T	PA-7150	1994	125	?|0.8	0.85	196	?|2048	1024	—	1.1b
	PCX-T'	PA-7200	1994	120	960	0.55	1.26	210	30	1024	2048	—	1.1c
	PCX-L	PA-7100LC	1994	60–100	?|0.75	0.9	201.6	7–11	—	1	2	1.1d
	PCX-L2	PA-7300LC	1996	132–180	?|0.5	9.2	260.1	?|64	64	0–8	1.1e
	PCX-U	PA-8000	1996	160–180	960	0.5	3.8	337.68	?|1024	1024	—	2.0
	PCX-U+	PA-8200	1997	200–240	960	0.5	3.8	337.68	?|2048	2048	—	2.0
	PCX-W	PA-8500	1998	300–440	1920	0.25	140	467	?|1024	512	—	2.0
	PCX-W+	PA-8600	2000		360–550		1920		0.25		140		467		?		1024		512		—		2.0
	PCX-W2	PA-8700(+)	2001		625–875		1920		0.18		186		304		<7.1@1.5 V		1536		768		—		2.0
	Mako	PA-8800	2003		800–100０		640０		０．13		300		361		？		768/core		768/core		０ or 32		２．０
	ＰＡ -８９００ |２００５ |８００－１１００ |６４００ |０．１３ |？ |？ |？ |７６８ / core |７６８ / core |０ or ６４ |２．０ |

See also

• Amiga Hombre chipset – Multimedia chipset based on PA-7150 for the Commodore Amiga
• Additional third-party PA-RISC processors from manufacturers such as Hitachi, Oki Electric Industry, and Winbond
• ARM architecture family – Rival RISC instruction set architecture introduced in the mid-1980s
• SPARC – Another competing RISC ISA from the mid-1980s

External links

• LostCircuits Overview of Hewlett Packard PA8800 RISC Processor
• HP documentation – Includes PDFs related to PA-RISC architecture
• OpenPA.net Extensive resource on PA-RISC processors and systems
• chipdb.org Collection of images showcasing various PA-RISC CPUs