PDP-10

DEC PDP-10 Registers
	General Purpose Registers
AC0	Register 0
	colspan="7" Program Counter and Status Flags

Digital Equipment Corporation (DEC)
Industry	Computer hardware
Founded	1957; 69 years ago
Founder	Ken Olsen, Harlan Anderson
Defunct	1998
Fate	Acquired by Compaq
Headquarters	Maynard, Massachusetts, United States
Products	PDP-10, DECsystem-10, DECSYSTEM-20, PDP-6, VAX
Number of employees	14000 (1980)

Digital Equipment Corporation (DEC) developed the PDP-10, a series of mainframe computers produced from 1966 until its discontinuation in 1983. During the 1970s, these systems were rebranded as DECsystem-10, coinciding with the widespread use of the TOPS-10 operating system.

The PDP-10's design is closely related to DEC’s earlier PDP-6, sharing a 36-bit word size and an expanded instruction set, but featuring significant enhancements in hardware design. A distinctive aspect is its byte instructions, which manipulate bit fields ranging from 1 to 36 bits, demonstrating a flexible interpretation of the term byte.

This computer family found extensive use in academic and research institutions such as Harvard’s Aiken Computation Laboratory, MIT’s AI Lab and Project MAC, Stanford’s SAIL, Computer Center Corporation (CCC), ETH (ZIR), and Carnegie Mellon University. It supported prominent operating systems including TOPS-10 and TENEX, which were instrumental in the early development of ARPANET. Consequently, the PDP-10 became an integral part of hacker culture and the history of academic computing.

Although DEC intended to continue the PDP-10 series, its market share was eventually eclipsed by DEC’s unrelated VAX superminicomputer line. The company officially ceased production of the PDP-10 in 1983, having sold around 1,500 DECsystem-10 units by 1980.

Models and technical evolution

The initial PDP-10 processor, known as the KA10, debuted in 1968. It utilized discrete transistor components housed in DEC's Flip-Chip module format along with semi-automated wire-wrapped backplanes. The KA10 operated with a cycle time of 1 μs and an addition operation time of 2.1 μs. In 1973, it was succeeded by the KI10 model, which employed transistor–transistor logic (TTL) SSI integrated circuits. The KL10 arrived in 1975, offering improved performance through emitter-coupled logic (ECL), microprogramming capabilities, and built-in cache memory. This model achieved approximately 1 megaflop on 36-bit floating-point matrix calculations, outperforming the contemporaneous VAX-11/750, albeit with somewhat smaller memory capacity.

In 1978, DEC released the KS10—a more compact and cost-efficient system based on TTL and Am2901 bit-slice technology that incorporated the PDP-11 Unibus for peripheral connectivity. Marketed under the DECSYSTEM-2020 designation within the DECSYSTEM-20 series, it targeted distributed processing environments as "the world's lowest cost mainframe computer system."

KA10

The KA10 supported a main memory capacity ranging from a minimum of 16 kilowords up to 256 kilowords (equivalent to 1,152 KB). It did not include built-in paging hardware; instead, memory management was handled through two sets of protection and relocation base and bounds registers. This approach allowed segmented address spaces supporting shareable code segments alongside read-write data areas—a scheme later adopted by Unix. Certain KA10 installations at MIT and BBN were upgraded with virtual memory capabilities and demand paging.

The KA10 had an approximate weight of . The highest-end uniprocessor variant was the 10/50 model, which debuted alongside the PA1050 software package. Additional configurations included the uniprocessor 10/40 and the dual-processor 10/55 models.

KI10

The KI10 introduced capabilities for paged memory management and expanded the physical addressing range to 4 megawords. This series includes models such as the 1060, 1070, and 1077, with the latter distinguished by its dual-CPU configuration.

KL10

The initial KL10 PDP-10 models, marketed under the DECsystem-10 name (including 1080 and 1088), utilized the original PDP-10 memory bus paired with external memory units—large cabinets that typically contained between 32 and 256 kWords of magnetic-core memory. In contrast, processors found in the DECSYSTEM-20 series (2040, 2050, 2060, 2065), often mistakenly referred to as "KL20," incorporate internal memory located within the CPU cabinet. The 10xx models employ taller PDP-10 enclosures, whereas the 20xx models use shorter ones. The primary distinctions between these groups involve their operating systems—TOPS-10 for the 10xx series and TOPS-20 for the 20xx—with some overlap in memory and input/output arrangements. Every ARPAnet TOPS-20 machine included an I/O bus designed to support the AN20 IMP interface. Both model lines were capable of running either TOPS-10 or TOPS-20 microcode alongside their corresponding operating systems.

Model B

The Model B enhancement for the 2060 processors eliminated the previous virtual address limit of 256 kWords by enabling support for up to 32 "sections," each containing 256 kWords. This upgrade also introduced substantial modifications to the instruction set architecture, effectively resulting in a distinct CPU design. The initial deployment of these features was in TOPS-20 release 3, with user mode extended addressing added in release 4. Subsequent versions beyond release 4.1 operate solely on Model B hardware. Additionally, TOPS-10 versions 7.02 and 7.03 utilize extended addressing when running on Model B machines (1090 or 1091) under TOPS-20 microcode.

MCA25

The MCA25 represented the final KL10 upgrade, converting a 2060 into a 2065 or a 1091 into a 1095. This enhancement improved performance for applications utilizing multiple memory sections.

Massbus

The KL10’s input/output structure is founded on DEC’s proprietary Massbus architecture. Unlike the open PDP-11 Unibus, Massbus was exclusive to DEC systems, which restricted third-party peripheral development. DEC positioned Massbus devices such as the RP06 disk drive at a higher price point compared to IBM-compatible alternatives. Notably, CompuServe engineered its own disk controller to function with Massbus while interfacing with IBM-style 3330 disk subsystems.

Front-end processors

KL series machines incorporate a PDP-11/40 front-end processor responsible for system initialization and monitoring tasks. The PDP-11 boots from a dual-ported RP06 disk drive or alternatively from an 8" floppy disk or DECtape, then initiates the main processor—typically booted from the same RP06 device. After startup, the PDP-11 continues to perform watchdog duties while the main processor operates.

Communication with IBM mainframes, including Remote Job Entry (RJE), was managed through DN61 or DN-64 front-end processors utilizing either a PDP-11/40 or PDP-11/34a.

KS10

The KS10 is an economical variant of the PDP-10 constructed using AMD 2901 bit-slice components along with an Intel 8080A microprocessor serving as control logic. Although equipped with most data paths found in Model B systems, the KS10 was intentionally restricted to Model A features as part of a market segmentation strategy that shortened its lifespan.

Its boot sequence mirrors that of the KL10: the 8080 control processor loads microcode from RM03, RM80, or RP06 disks or magnetic tape before activating the main processor. Following boot-up, the 8080 manages console functions and remote diagnostic serial communications.

Magnetic Tape Drives

The TM10 Magnetic Tape Control subsystem was compatible with the following tape transports:

TU20 Magnetic Tape Transport operating at 45 inches per second (ips)
TU30 Magnetic Tape Transport operating at 75 ips
TU45 Magnetic Tape Transport operating at 75 ips

Configurations could include up to eight tape drives, supporting IBM-standard 7-track or 9-track tapes. Both the TU20 and TU30 were available in two variants: A (9-track) and B (7-track), all capable of handling tapes with densities of 200, 556, and 800 bits per inch (BPI).

There were two versions of the TM10 controller:

TM10A utilized cycle-stealing to access the PDP-10 memory through the KA10 Arithmetic Processor
TM10B interfaced with memory via a DF10 Data Channel, avoiding cycle-stealing from the KA10 Arithmetic Processor

Instruction Set Architecture

Across models from the PDP-6 through the KL-10 and KS-10, the user-mode instruction set architecture remained mostly unchanged. The main evolution appeared in the KL-10 with multi-section extended addressing, which modified how effective addresses are generated (outlined briefly below). The architecture generally employs 36-bit words and instructions, alongside 18-bit addressing.

Registers

The system provides sixteen general-purpose registers, each 36 bits wide. Except for register zero, the right half of each register can function as an index register. Certain instructions operate on pairs of registers. The "PC Word" register is divided into an 18-bit program counter and a left-side block of thirteen processor status flags, separated by five zero bits. Condition flags indicating arithmetic outcomes such as overflow are accessible through a limited set of instructions.

In the original KA-10 models, these registers are mapped as the initial sixteen words of main memory. An optional "fast registers" hardware enhancement relocates these registers physically inside the CPU while preserving compatibility with memory addressing. Some software exploited this feature by treating registers as a form of CPU cache for code—loading instructions into registers and jumping to those addresses—an approach notably employed by Maclisp for its garbage collector. Later PDP-10 variants integrated these registers directly within the CPU hardware.

Supervisor mode

The system functions in two distinct modes: supervisor and user. Unlike user mode, supervisor mode permits input/output operations. Transitions from user to supervisor mode are triggered through Unimplemented User Operations (UUOs), which intercept undefined hardware instructions. This mechanism also enables the emulation of instructions missing in more cost-effective models.

Data types

The architecture inherently supports 36-bit two's complement integers, 36-bit floating-point numbers, and halfword data types. Extended precision 72-bit floating-point values can be handled via sequences of multiple instructions. Specialized instructions exist for managing byte pointers and defining bounded memory areas, which aid in stack-oriented memory allocation.

Instructions

Instructions are contained within 36-bit words and are categorized into two formats: general instructions and input/output instructions.

General instructions utilize the first 9 bits (leftmost) as the opcode, with many opcodes reserved for future extensions such as hardware floating-point units. Bits 9 through 12 identify a register number. Input/output instructions are distinguished by bits 0 to 2 set to binary 111 (decimal 7), bits 3 to 9 specifying the device number, and bits 10 to 12 indicating the opcode.

The remaining bits from position 13 to 35 represent the "effective address" (E), composed of a base address (Y) occupying bits 18 to 35 combined with an optional index register (X) from bits 14 to 17. Bit 13 (I) signals indirection, meaning the effective address points to another memory location rather than directly accessing data. Multiple levels of indirection can be chained until an indirect bit set to zero is encountered.

In supervisor mode, addresses correspond directly to physical memory locations; in user mode, addresses undergo translation initially via a segmented "high" and "low" memory scheme, later evolving into paged memory management for handling non-contiguous address spaces. The CPU's general-purpose registers are accessible as memory addresses ranging from 0 to 15.

General instructions

General instructions fall into three primary categories: arithmetic/logical/move operations; conditional jumps; and conditional skips (which may produce side effects), along with several smaller instruction groups.

Arithmetic, logical, and move operations come in variants such as immediate-to-register, memory-to-register, register-to-memory, combined register-and-memory-to-both, or memory-to-memory transfers. Registers can be referenced as memory locations, enabling register-to-register operations. For instance, ADD instruction variants include ADDI (adding an 18-bit immediate value to a register), ADDM (adding a register’s contents to a memory location), and ADDB (adding a register’s contents to memory and storing the result back into the register). More advanced instructions like HLROM operate on halfwords for linked list manipulations similar to Lisp’s CAR (HLRZ) and CDR (HRRZ) functions.

Conditional jump instructions evaluate register values to determine whether to branch based on comparisons. Their mnemonics generally begin with JUMP; for example, JUMPA means "always jump," whereas JUMP means "never jump," effectively acting as no-operations in some cases. The instruction JUMPN A,LOC causes a jump if register A is non-zero. The JRST instruction examines the processor’s condition register and executes faster than JUMPA on KA10 and KI10 models.

Conditional skip instructions compare values between registers and memory locations to decide whether to skip the following instruction depending on the comparison outcome. For example, CAMN A,LOC skips execution if register A does not equal the content at location LOC. TLCE A,LOC applies a mask from LOC on the left half of register A; if all masked bits are zero, it skips the next instruction and complements those masked bits in the register.

Additional smaller instruction classes include shift/rotate operations and procedure call instructions. Stack-related commands such as PUSH and POP along with their call variants PUSHJ and POPJ provide mechanisms for stack management. Byte-oriented instructions utilize a special indirect word format that allows extraction or storage of arbitrarily sized bit fields while advancing pointers accordingly.

Input/output instructions

Unlike the PDP-11 and subsequent DEC systems, the PDP-10 does not utilize memory-mapped I/O. Instead, it features a separate set of instructions dedicated to device data transfer, identified by a 7-bit device identifier (bits 3 through 9), which enables support for up to 128 devices. Data movement can be executed either one word at a time using DATAO/DATAI instructions or in blocks via BLKO/BLKI commands.

In block transfer mode, the word referenced by register E is divided into two 18-bit segments: the right segment specifies the memory address for data transfer, while the left segment acts as a counter. Each invocation of a block instruction increments both fields, performs a DATAO or DATAI operation, then evaluates the counter—if it remains non-zero, the following instruction is skipped; if zero, normal execution proceeds (typically resulting in a loop). This hardware-assisted looping mechanism enhances repeated I/O efficiency by minimizing memory fetch cycles.

Additional I/O operations include CONO and CONI instructions used for writing to and reading from device condition registers. The CONSZ instruction executes a CONI, applies a mask against the value in register E, and if the result is zero (testing only the lower 18 bits), it skips the next instruction—functionally resembling BLK commands to facilitate rapid device status verification.

Interrupt handling

The CONO instruction also configures a device’s interrupt priority level using three bits (33–35), defining levels from 0 to 7. Priority level 1 holds the highest precedence; if multiple devices interrupt simultaneously, the device with the lower number is serviced first. Setting priority level 0 disables interrupts for that device, preventing it from interrupting processor execution even if an interrupt is signaled.

Each device channel occupies two memory locations at addresses 40+2N and 41+2N (where N is the channel number). For instance, channel 1 corresponds to addresses 42 and 43. When an interrupt is accepted (assuming no higher-priority interrupt is active), processing halts at the next memory read and resumes at the address stored in the first location. To clear the interrupt, the handler must execute a CONO, DATA, or BLK instruction. For BLKI or BLKO commands, if the incremented counter is not zero, the interrupt is immediately cleared; otherwise, processing continues with the second instruction—providing an efficient medium-speed direct memory access approach.

Two specific device numbers serve unique functions: Device 0 represents the front-panel console (reading returns switch settings; writing controls indicator lamps), while Device 4 corresponds to the "priority interrupt," which can be read using CONI to obtain additional interrupt information.

Extended addressing

Processors supporting extended addressing organize memory into multiple "sections." An 18-bit address represents a "local address," indicating an offset within a section. A "global address" consists of 30 bits: a 12-bit section identifier combined with an 18-bit offset inside that section. Registers may contain either an 18-bit local index or a full 30-bit global index.

Indirect words come in two forms: "local indirect words," where the highest bit is set and include an indirect bit, register code, and an 18-bit displacement; and "global indirect words," where this bit is clear and comprise an indirect bit, register code, and a 30-bit displacement. Calculating effective addresses yields both a 12-bit section number and an 18-bit offset within that segment.

Operating systems

The PDP-10's initial operating system, originally named "Monitor," was subsequently rebranded as TOPS-10, while the PDP-10 hardware line became known as the DECsystem-10. Early iterations of Monitor and TOPS-10 served as a foundation for systems like Stanford's WAITS and the CompuServe time-sharing platform.

Certain PDP-10 users opted to build their operating systems by integrating components developed externally to DEC, enabling tailored solutions to meet specific organizational requirements. Advanced internal development teams at commercial time-sharing providers such as CompuServe, On-Line Systems, Inc. (OLS), and Rapidata independently customized their software environments. The user group DECUS played a key role in facilitating software exchange among PDP-10 operators.

BBN created an alternative OS named TENEX, which gained traction within research institutions. DEC later adapted TENEX for the KL10 model, enhancing it and releasing it as TOPS-20, which powered the DECSYSTEM-20 series.

MIT, recognized for CTSS, also developed ITS (Incompatible Timesharing System) to operate on their PDP-6 and subsequently modified PDP-10 machines.

Tymshare developed TYMCOM-X, a derivative of TOPS-10 that incorporated a page-oriented file system similar to that found in TOPS-20.

Programming languages

From 1967 through 1975, DEC provided support for DECsystem-10 FORTRAN IV (F40) on the PDP-10 platform.

Other programming languages supported included MACRO-10 (an assembly language macro assembler), COBOL, BASIC, and AID under multiprocessing and swapping monitor environments.

Additional programming languages such as LISP and SNOBOL were accessible at institutions like Hatfield Polytechnic circa 1970.

Clones

During 1971–1972, researchers at Xerox PARC, frustrated by management’s refusal to acquire a PDP-10, engineered two PDP-10 clones called MAXC (Multiple Access Xerox Computer), named in tribute to Max Palevsky who had sold SDS to Xerox. MAXC operated a customized version of TENEX. Other third-party vendors producing PDP-10 compatible systems, including Foonly, Systems Concepts, and XKL, achieved only modest commercial penetration.

Use by CompuServe

CompuServe maintained one of the largest installations of DECsystem-10 computers, comprising over 200 loosely connected systems distributed across three data centers in Columbus, Ohio. Initially relying on DEC hardware, CompuServe shifted to plug-compatible machines supplied by Systems Concepts after DEC prioritized the VAX product line. As of January 2007, a small number of PDP-10 systems remained in use at CompuServe for billing and routing purposes.

To enhance operational efficiency, CompuServe’s engineering team redesigned the KL-series power supplies, achieving a 50% reduction in power consumption. They offered this improved design royalty-free to DEC should it be incorporated into future KL models; however, DEC declined the proposal. Furthermore, CompuServe replaced hundreds of incandescent status lamps on KI10 cabinets with LED modules, significantly lowering electricity usage, heat generation, and maintenance demands. Digital later implemented this LED retrofit worldwide. The adjacent image depicts an MF10 memory panel fitted with LEDs for museum exhibition; comparable indicator arrays were not present on KL or KS processors themselves.

Cancellation and Impact

DEC's VAX superminicomputers, which evolved from the PDP-11 series, ultimately replaced the PDP-10 as DEC shifted its software development efforts toward the more commercially successful VAX lineup. In 1983, DEC officially terminated the PDP-10 product series, canceling projects such as the Jupiter initiative—a high-performance PDP-10 processor under development—and the Minnow, a prototype desktop PDP-10.

This move brought an end to official support for ITS and its associated technical communities. Nevertheless, by the 1990s, proficiency with the PDP-10 was regarded as a badge of honor among experienced hackers.

Certain PDP-10 assembly instructions like LDB and DPB continue to influence Common Lisp functions today. The 36-bit architecture of both the PDP-6 and PDP-10 was intentionally designed to accommodate two 18-bit Lisp pointers within a single word efficiently.

The PDP-10 was the platform for several groundbreaking computer games, including Will Crowther's Adventure, Don Daglow's pioneering computer baseball game (1971) and Dungeon (1975), Walter Bright's Empire, as well as the original MUD developed by Roy Trubshaw and Richard Bartle. The text adventure Zork was also created on this system, with Infocom using PDP-10 machines extensively during its development and testing phases.

Notably, Bill Gates and Paul Allen developed Altair BASIC on a PDP-10 at Harvard by running an Intel 8080 simulator on it, repurposing its assembler as a cross assembler. This work preceded their establishment of Microsoft.

Emulation and Simulation

The SIMH emulator replicates all models of the PDP-10 CPU on Windows and Unix platforms, allowing users to operate TOPS-10 or TOPS-20 using original DEC distribution tapes. Additionally, operating systems such as ITS and WAITS are available for SIMH emulation. A functional replica of the KA10 processor’s front panel operates SIMH emulation on a Raspberry Pi device.

Ken Harrenstien’s KLH10 software provides emulation of KL10B processors with extended addressing capabilities (supporting up to 4 megawords of memory) and KS10 processors (with 512 kilowords of memory) on Unix-like systems. The KL10 emulation supports microcode version 442, enabling operation of the final releases of TOPS-10 and TOPS-20. Meanwhile, KS10 emulation supports ITS microcode version 262 and DEC’s version 130 microcode for KS TOPS-10 and TOPS-20 systems.

External links

36 Bits Forever!
PDP-10 Models — CPU and model details
PDP-10 resources
PDP-10 Miscellany
Life in the Fast AC's
Columbia University DEC PDP-10 page
Panda Programming TOPS-20 page
Online PDP-10 and related systems at SDF's Interim Computer Museum (includes systems from the Paul Allen collection at Living Computers: Museum + Labs)
Empire for the PDP-10 (FORTRAN-10 source code) from Classic Empire
PDP-10 software archive at Trailing Edge
The Personal Mainframe ad
Computer World ad for Personal Mainframe
PDP-10 documentation at BitsVers

Newsgroups

alt.sys.pdp10