PDP-6

Digital Equipment Corporation (DEC)

Industry	Computer hardware
Founded	May 16, 1957 (1957-05-16) in Massachusetts, United States
Headquarters	Maynard , United States
Products	PDP-6, PDP-1, PDP-4, PDP-5, PDP-10

The PDP-6, or Programmed Data Processor model 6, was introduced by Digital Equipment Corporation (DEC) in 1963 and became available to customers by mid-1964. This system extended DEC's earlier 18-bit architecture to a 36-bit word length, matching the word size typical of large-scale computers such as IBM mainframes. The PDP-6 retained the germanium transistor-based System Module design utilized in previous DEC models like the PDP-1 and PDP-4.

Engineered with real-time computing in mind, the PDP-6 supported 36-bit words alongside 18-bit addressing, which was particularly efficient for storing cons cells in the Lisp environment. This made it a preferred platform for artificial intelligence research projects, including MIT's Project MAC. It incorporated integrated floating point instructions, a feature that was relatively rare at that time. Despite these advancements, its intricate design, substantial price range ($120,000–$300,000), and reliance on early transistor technology resulted in limited commercial success, with only 23 units sold.

A significant contribution of the PDP-6 to DEC’s business was its evolution into a redesign employing contemporary silicon transistors and Flip-Chip module packaging techniques. This transformation gave rise to the more dependable and cost-effective PDP-10. The PDP-10 maintained almost identical instruction sets to the PDP-6 but achieved much higher sales volumes, with roughly 1,500 units distributed.

History

DEC’s earliest products consisted of plug-in circuit boards known as Digital Laboratory Modules, designed for digital logic applications. These modules served as foundational components for the PDP-1, which was constructed from numerous System Building Blocks or System Modules.

The PDP-1 operated on an 18-bit word size and was both smaller and less expensive compared to the prevalent 36-bit computers at the time, retailing at . Following this, DEC released the PDP-4 as a more compact and affordable iteration of the PDP-1, while the 12-bit PDP-5 further reduced costs to approximately .

The introduction of the PDP-6 marked DEC’s entry into the realm of large-scale computers featuring 36-bit words, aligning with competitors such as IBM and Honeywell. It was also DEC’s first system to be shipped with manufacturer-supported timesharing capabilities. Nevertheless, its complexity and high price contributed to slow sales, limiting production to only 23 units. Despite these challenges, the PDP-6 helped establish DEC’s footprint in academic and scientific sectors and fostered valuable customer feedback and engineering expertise that influenced future innovations.

Initially, DEC had intended to phase out 36-bit systems but later reversed this decision by launching the enhanced PDP-10 in 1966. The PDP-10 maintained compatibility with its predecessor while delivering twice the performance, supporting both timesharing and batch processing environments along with extensive expansion capabilities. This model achieved substantial market success with around 1,500 units sold.

Architecture

The addressing scheme remained at 18-bit, consistent with earlier DEC machines, enabling access to up to 256 kwords of main memory, equivalent to approximately one megabyte today. Memory was built using magnetic core technology; a standard configuration typically comprised 32,768 words (roughly 144 kB by current standards). The use of a 36-bit word length allowed for storing two separate 18-bit addresses within a single memory location, which was particularly advantageous for representing a cons cell in Lisp, allowing both storage and manipulation within one word.

The instruction set employed a "one-and-a-half address" format: each instruction occupied a 36-bit word where the most significant 9 bits encoded the opcode, followed by 4 bits specifying one of sixteen registers, and then an 18-bit address field. For instance, an instruction might add the content at memory address 1234 to register number 4, combining one complete address reference with one register operand.

Bits numbered 13 through 17 provided supplementary control features: bit 13 signaled indirect addressing mode—whereby the content at the given address was interpreted as another memory address from which data would be retrieved. This mechanism facilitated efficient traversal through tables by modifying pointers stored in memory. The remaining four bits were used to select a secondary register serving as an index register, enabling indexed addressing via rapid-access registers instead of slower main memory references.

In the PDP-6 architecture, registers corresponded to the first sixteen locations in main memory. Many systems optionally included Type 162 "Fast Memory," which implemented these registers using discrete-transistor flip-flops capable of operating at speeds approximately four times faster than conventional core memory.

Hardware

The PDP-6 had a weight of approximately , which increased to when equipped with the "Fast Memory" option.

A significant hardware difficulty involved the 6205 board—a sizable module measuring 11 by 9 inches, each containing a single bit of the arithmetic register (AR), memory buffer (MB), and multiplier-quotient register (MQ). The central processing unit consisted of 36 such boards. Each board incorporated 88 transistors, featured double-sided printed circuit etching, and included multiple connectors, making replacements complicated and susceptible to cascading malfunctions. Powering down the PDP-6 frequently resulted in failure of at least one 6205 board.

This hardware experience led to design changes in subsequent PDP-10 models (KA10 and KI10), which initially employed only smaller circuit boards; larger boards were later reintroduced with the KL10 variant.

Operating system

The PDP-6 provided time-sharing capabilities by utilizing a status bit to alternate between "Executive" and "User" modes, restricting input/output (I/O) access during user mode. It incorporated a relocation and protection register to confine a user's address space within main memory. An additional register for shareable "high segments" was introduced later on the PDP-10. Its main operating system was an early iteration that eventually developed into TOPS-10, with various installations customizing the software, which was distributed in source code form. The MIT-developed Incompatible Timesharing System (ITS) also originated on this machine.

Although time-sharing could operate on the PDP-6 without a disk drive, configuring it with four dual DECtape drives allowed support for roughly 4 to 6 concurrent users. Incorporating a single disk drive enabled true real-time sharing for between 20 and 30 users.

Museum

The PDP-6 owned by Stanford University was displayed at DECUS in 1984 before being relocated to a DEC storage facility. There is no documentation indicating it was ever donated to the Computer Museum, which operated independently from DEC at that period. In the late 1990s, Compaq contributed DEC’s internal archives to The Computer Museum History Center, including the Fast Memory cabinet from Stanford’s PDP-6. Nevertheless, no evidence exists that any components sold at the Boston computer museum gift shop originated from this system or that the museum ever possessed it.

External links

• PDP-6 Serial numbers
• DEC's PDP-6 was the world's first commercial time-sharing system Gordon Bell interview at the Smithsonian
• USENET alt.sys.pdp10 postings comparing the PDP-6 with the KA10
• PDP-6 DIGITAL Computing Timeline, Digital Equipment Corporation
• Tops 10 DIGITAL Computing Timeline, Digital Equipment Corporation
• The PDP-6 at Stanford
• The PDP-6 Home Page by Tom Knight