POWER5
| Company type | Microprocessor |
|---|---|
| Industry | Semiconductor |
| Predecessor | POWER4 |
| Founded | 2004 |
| Founder | IBM |
| Products | POWER5 microprocessor, POWER5+ microprocessor |
| Parent | IBM |
The POWER5 microprocessor, developed and manufactured by IBM, represents an advancement over the earlier POWER4 model. Enhancements include the introduction of simultaneous multithreading (SMT) capabilities and the integration of an on-chip memory controller. This dual-core CPU supports one physical thread per core and two logical threads each, resulting in a total of two physical and four logical threads.
History
Initial technical specifications were disclosed at the 2003 Hot Chips event, with a comprehensive overview presented later that year at the Microprocessor Forum 2003. Launched in 2004, the POWER5 was exclusively available to IBM and its affiliates, aimed at the premium enterprise server segment where it competed with Intel's Itanium 2, Sun Microsystems' UltraSPARC IV, and Fujitsu's SPARC64 V. Its successor, the POWER5+, followed in 2005.
Description
Derived from the POWER4 design, the POWER5 incorporated two-way multithreading by replicating critical components such as the return stack, program counter, instruction buffer, group completion unit, and store queue to handle distinct threads. Although several resources like register files and execution units are shared, each thread maintains its own register set. The SMT feature enables concurrent execution of two threads per core but can be disabled to better suit specific workload demands.
To mitigate performance degradation due to resource sharing, the register files were increased to 120 integer and floating-point registers respectively (up from 80 integer and 72 floating-point registers in the POWER4). The floating-point issue queue expanded from 20 to 24 entries. The L2 unified cache size was enlarged to 1.875 MB with a 10-way set associativity. Importantly, the unified L3 cache was relocated on-package, offering 36 MB shared between cores and accessed through two unidirectional 128-bit buses operating at half the core frequency.
The embedded memory controller supports up to 64 GB of DDR and DDR2 RAM via high-speed serial buses connected to external buffers interfacing with DIMMs.
Fabricated using IBM’s 0.13 μm silicon-on-insulator CMOS technology featuring eight layers of copper interconnects, the POWER5 chip contains 276 million transistors across a die measuring 389 mm². Packaging options include a dual chip module (DCM) consisting of one POWER5 die plus an L3 cache die, or a multi-chip module (MCM) that integrates four POWER5 dies alongside four L3 cache dies within a 95 mm square footprint.
In advanced system configurations, multiple POWER5 processors can be interconnected through IBM’s Virtual Vector Architecture (ViVA) technology to function collectively as a single vector processor, significantly boosting computational efficiency for enterprise workloads.
POWER5+
Released on October 4, 2005, the POWER5+ is an improved iteration of the POWER5. It features reduced power consumption thanks to a smaller 90 nm manufacturing process that decreased die size from 389 mm² to 243 mm². Initial clock frequencies ranged from 1.5 to 1.9 GHz, with subsequent models achieving speeds up to 2.3 GHz by July 2006.
The POWER5+ was offered in the same packaging formats as its predecessor as well as a quad-chip module (QCM), which combines two POWER5+ dies with two L3 cache dies and operates between 1.5 and 1.8 GHz.
Products
IBM incorporates DCM and Multi-Chip Module (MCM) POWER5 processors within its System p and System i server families, DS8000 storage systems, as well as advanced Infoprint printers. The DCM POWER5 also powers IBM's IntelliStation POWER 285 workstation. Among external users, Groupe Bull integrates these processors in Escala servers, while Hitachi utilizes them in SR11000 models, which support configurations of up to 128 POWER5+ processors and are featured on the TOP500 supercomputer list. For its System p5 510Q, 520Q, 550Q, and 560Q servers, IBM deploys the POWER5+ QCM processor.