POWER9
| Company type | Microprocessor line |
|---|---|
| Industry | Semiconductor |
| Predecessor | POWER8 |
| Founded | August 2016 |
| Headquarters | Armonk , United States |
| Products | POWER9 microprocessors |
| Owner | IBM |
| Website | www |
POWER9 represents a line of superscalar, multithreaded, multi-core microprocessors created by IBM, utilizing the Power ISA instruction set. Introduced in August 2016, these processors are fabricated using a 14 nm FinFET technology and are available in configurations featuring 12 or 24 cores. They are engineered to support both scale-out and scale-up workloads. The architecture is openly licensed and can be adapted by participants in the OpenPOWER Foundation.
The POWER9 platform powers Summit, which as of June 2024, ranks ninth among the world’s fastest supercomputers, combining POWER9 CPUs with Nvidia Tesla GPU accelerators.
Core
The POWER9 core comes in two editions: a four-thread SMT4 and an eight-thread SMT8. Each core is composed of multiple slices, where each slice is a 64-bit single-threaded core equipped with load/store units, integer units, and vector scalar units. Two of these slices form a super-slice. The SMT4 core contains 32 KiB L1 instruction cache and 32 KiB L1 data cache, along with an instruction fetch unit (IFU) and an instruction sequencing unit (ISU) that supplies two super-slices. In contrast, the SMT8 core doubles these elements to feed four super-slices. Consequently, both 12-core and 24-core POWER9 processors incorporate a total of 96 slices with equivalent L1 cache sizes.
Featuring a 12-stage pipeline—shorter by five stages compared to POWER8—POWER9 cores aim for clock speeds near 4 GHz. This generation is the first to implement aspects of Power ISA version 3.0, including VSX-3 instructions. Its modular design allows flexibility for different processor models and manufacturing processes. Integrated co-processors manage compression and encryption tasks, complemented by a substantial low-latency eDRAM L3 cache.
POWER9 debuts the eXternal Interrupt Virtualization Engine (XIVE), an advanced interrupt controller architecture that supersedes simpler mechanisms used from POWER4 through POWER8. This interrupt controller design is also incorporated in Power10 processors.
Scale out / scale up
- The IBM POWER9 SO (scale-out) model targets dual-socket configurations, delivering up to 120 GB/s bandwidth directly connected to DDR4 memory; this variant was introduced in 2017.
- The IBM POWER9 SU (scale-up) version supports systems with four or more sockets for large NUMA implementations, offering up to 230 GB/s bandwidth to buffered memory via the PowerAXON 25 GT/sec Link interface.
Both versions may feature cores disabled due to manufacturing yield considerations; for instance, Raptor Computing Systems initially offered 4-core variants, while IBM’s AC922 systems launched with up to 22 active cores despite being based on 24-core dies.
I/O
POWER9 incorporates comprehensive on-chip features designed to improve off-chip input/output (I/O) throughput:
- The SO variant includes integrated DDR4 memory controllers for direct RAM connections, whereas the SU variant utilizes the external Centaur architecture, which provides high-performance eDRAM L4 cache along with DDR4 memory controllers.
- Bluelink interconnect technology supports close coupling with Nvidia graphics processors through NVLink v.2 and facilitates accelerators using the OpenCAPI standard.
- Standardized PCIe v.4 interfaces enable connectivity with ASICs, FPGAs, and peripheral devices, alongside compatibility with CAPI 1.0 and 2.0 devices originally designed for POWER8.
- Multiprocessor interconnects allow symmetric multiprocessing by linking multiple POWER9 CPUs within a single motherboard or across nearby chassis.
Chip Variants
POWER9 processors are available in two primary core configurations: Scale Out and Scale Up. The SMT4 cores are tailored for PowerNV systems operating Linux without PowerVM, whereas the SMT8 cores are intended for environments utilizing PowerVM. Scale Out processors accommodate directly connected memory, while Scale Up processors are engineered for systems featuring more than two CPU sockets and utilize buffered memory.
| PowerNV | PowerVM | |
|---|---|---|
| 24 × SMT4 core | 12 × SMT8 core | |
| Scale Out | Nimbus | unknown |
| Scale Up | Cumulus |
Module Types
According to IBM's OpenPOWER Portal, the Nimbus chip is supported by three module types, with the Scale-Out SMT8 variant also employing the LaGrange module/socket:
- Sforza – 50×50 mm footprint, featuring 4 DDR4 memory channels, 48 PCIe lanes, and a single XBus 4B interface
- Monza – 68.5×68.5 mm size, equipped with 8 DDR4 channels, 34 PCIe lanes, one XBus 4B connection, and 48 OpenCAPI lanes
- LaGrange – measures 68.5×68.5 mm, includes 8 DDR4 channels, 42 PCIe lanes, dual XBus 4B links, and 16 OpenCAPI lanes
The Sforza modules utilize a land grid array (LGA) socket with 2601 pins.
Raptor Computing Systems / Raptor Engineering
- Talos II – a dual-socket workstation/server platform based on POWER9 SMT4 Sforza CPUs; available in configurations including 2U rackmount server, 4U rackmount server, tower case, or EATX motherboard. It is promoted as a secure system offering full user control through free and open-source firmware and software. Initially launched with chip options of 4-core, 8-core, 18-core, and 22-core models prior to availability of higher core counts.
- Talos II Lite – a single-socket variant of the Talos II motherboard utilizing the same printed circuit board.
- Blackbird – a microATX single-socket system featuring SMT4 Sforza processors (up to an 8-core model with a thermal design power of 160 W), supporting between 4 and 8 cores and up to 256 GiB of RAM across two memory slots.
Google–Rackspace Collaboration
- Barreleye G2 / Zaius – a two-socket server platform deploying LaGrange processors; both utilize the Zaius POWER9 motherboard and chassis designed for open compute infrastructure.
IBM Systems
- Power System AC922 – a 2U system housing dual POWER9 SMT4 Monza processors; supports up to six Nvidia Volta GPUs along with two CAPI 2.0 attached accelerators and up to 1 TiB DDR4 memory. Also known as "Witherspoon" or "Newell," it is optimized for AI acceleration, high-performance data analytics (HPDA), and high-performance computing (HPC) workloads.
- Power System L922 – a compact 2U platform with one or two POWER9 SMT8 processors offering between 8 to 12 cores each; supports up to 4 TiB DDR4 RAM running PowerVM on Linux.
- Power System S914 – a larger 4U configuration with a single POWER9 SMT8 processor ranging from 4 to 8 cores; accommodates up to 1 TiB DDR4 RAM and runs PowerVM supporting AIX, IBM i, or Linux.
- Power System S922 – housed in a 2U chassis with one or two POWER9 SMT8 CPUs providing between 4 and 11 cores per processor; supports up to 4 TiB DDR4 memory under PowerVM for AIX, IBM i, or Linux.
- Power System S924 – a larger scale system in a 4U form factor containing two POWER9 SMT8 processors each with between 8 and 12 cores; supports up to 4 TiB DDR4 RAM running PowerVM compatible with AIX, IBM i, or Linux.
- Power System H922 – a versatile 2U system equipped with one or two POWER9 SMT8 CPUs offering between 4 and 10 cores each; supports up to 4 TiB DDR4 RAM optimized primarily for SAP HANA on Linux while allowing up to approximately one-quarter of resources for AIX or IBM i workloads.
- Power System H924 – a larger-scale SAP HANA-focused system in a 4U chassis featuring two POWER9 SMT8 processors each having between 8 and 12 cores; supports up to 4 TiB DDR4 RAM with additional AIX/IBM i support.
- Power System E950 – housed in a 4U enclosure supporting two to four POWER9 SMT8 processors with core counts ranging from eight to twelve per CPU; offers up to sixteen TiB buffered DDR4 memory.
- Power System E980 – scalable system consisting of up to four separate 4U units equipped with four to sixteen POWER9 SMT8 CPUs in total; each CPU contains between eight and twelve cores and supports as much as sixty-four TiB buffered DDR4 RAM.
- Hardware Management Console 7063-CR2 – a compact management appliance sized at one rack unit containing a single six-core POWER9 SMT8 processor paired with between sixty-four and one hundred twenty-eight GB DDR4 RAM dedicated to system administration tasks.
Penguin Computing
- Magna PE2112GTX – A 2U, dual-socket server designed for high-performance computing applications utilizing LaGrange processors. This system is produced by Wistron.
IBM supercomputers
- Summit and Sierra – Developed through a collaboration between the U.S. Department of Energy, Oak Ridge and Lawrence Livermore National Laboratories, IBM, and Nvidia, these supercomputers incorporate POWER9 CPUs alongside Nvidia Volta GPUs. Both were planned for release in 2017. Sierra employs IBM’s Power Systems AC922 compute nodes. The initial Summit racks were delivered to Oak Ridge National Laboratory on July 31, 2017.
- MareNostrum 4 – Within the emerging technologies segment of the fourth MareNostrum supercomputer, one cluster integrates POWER9 processors with Nvidia Volta GPUs, targeting performance exceeding 1.5 petaflops. This segment serves to evaluate innovative technologies for upcoming MareNostrum iterations.
Operating system support
POWER9 processors are compatible with FreeBSD, IBM AIX, IBM i, Linux (both with and without PowerVM), as well as OpenBSD.
Support for the Linux kernel commenced with version 4.6 released in March 2016.
Since 2018, several Linux distributions including Red Hat Enterprise Linux (RHEL), SUSE Linux Enterprise Server (SLES), Debian, Ubuntu, and CentOS have provided POWER9 support.
The GNU Guix package manager offers compatibility with POWER9; however, comprehensive support for the Guix System Distribution remains in Technology Preview status.