Power10
| File:IBM Power10 logo.svg Power10 logo | |
| Company type | Microprocessor series |
|---|---|
| Industry | Semiconductor |
| Founded | August 2020 |
| Headquarters | Armonk , United States |
| Products | Power10 microprocessors |
| Parent | IBM |
Power10 represents a superscalar, multi-core, multithreaded microprocessor series built upon the open source Power ISA. It was unveiled at the Hot Chips conference in August 2020 and became widely accessible starting September 2021 within the IBM Power10 Enterprise E1080 server.
This processor incorporates 15 active cores, with an extra spare core included during fabrication to economically mitigate yield challenges.
Manufactured by Samsung utilizing a 7 nm technology node, Power10 chips contain 18 metal layers and house 18 billion transistors on a silicon die measuring 602 mm2.
Notable advancements encompass enhanced energy efficiency, upgraded memory and input/output subsystems, along with dedicated enhancements for accelerating artificial intelligence (AI) processing tasks.
Design
Compared to its predecessor, POWER9, each Power10 core approximately doubles the number of functional units. The core facilitates eight-way simultaneous multithreading (SMT8) and integrates 48 KB instruction and 32 KB data L1 caches, a 2 MB L2 cache, plus a substantial 4096-entry translation lookaside buffer (TLB). Latency for accessing cache levels and TLB entries has been significantly minimized. Each core is composed of eight execution slices, each equipped with one floating-point unit (FPU), arithmetic logic unit (ALU), branch predictor, load–store unit, and an SIMD engine that executes 128-bit instructions introduced by Power ISA version 3.1’s prefix/fuse instruction set. Each slice manages up to 20 instructions simultaneously, supported by a centralized 512-entry instruction table, and supplied by broad load/store queues. Branch prediction accuracy has been doubled through architectural improvements. To accelerate SIMD workloads, especially matrix multiplication in AI inference, each core includes four matrix math assist (MMA) units that deliver a twentyfold increase in performance.
The processor is architected as two "hemispheres," each containing eight cores sharing a combined 128 MB L3 cache across all sixteen cores. Due to manufacturing yield considerations, at least one core is disabled per chip, resulting in 15 functional cores and a reduced L3 cache size of 120 MB. Additionally, the chip integrates eight cryptographic accelerators supporting algorithms such as AES and SHA-3.
Power consumption is cut in half relative to POWER9 through refined clock gating techniques, microarchitectural enhancements, and optimized fuse/prefix instruction implementations. Coupled with up to a 30% increase in computational efficiency, Power10 achieves approximately 2.6 times superior performance per watt. Dual-core modules can attain up to three times the processing speed within the same power envelope.
With SMT8 enabled, a processor featuring 15 cores exposes 120 logical processors to the operating system, scaling further to handle up to 240 concurrent threads on dual-chip modules per socket.
I/O
Power10 introduces revamped memory and I/O architectures leveraging the open standards of the Coherent Accelerator Processor Interface (OpenCAPI) and Open Memory Interface (OMI). By employing serial communication protocols for off-chip memory controllers, it reduces signal lane requirements while increasing bandwidth and allowing flexible support for various memory technologies.
Supported memory types span from DDR3 through DDR5, GDDR, HBM, and Persistent Storage Memory, customizable according to client specifications:
- DDR4 – maximum capacity of 16 TiB, bandwidth reaching 410 GB/s, latency around 10 ns
- GDDR6 – bandwidth up to 800 GB/s
- Persistent storage memory – scalable up to 2 PB
Data encryption is enforced throughout all stages—from main memory through accelerators and cluster nodes to data at rest—without compromising performance.
The PowerAXON technology facilitates communication across chips, systems, and OpenCAPI buses for accelerators, I/O devices, and cache-coherent peripherals. It orchestrates node interactions within clusters supporting up to sixteen sockets for single-chip modules or four sockets for dual-chip modules. This architecture enables Memory Inception, allowing load/store operations over clusters with aggregated RAM capacities up to 2 PB.
Both OMI and PowerAXON support off-chip data transfer speeds of up to 1 TB/s.
Power10 incorporates support for PCIe 5, with single-chip modules offering 32 lanes and dual-chip modules providing 64 lanes. IBM discontinued support for NVLink, as PCIe 5.0 delivers adequate bandwidth for Power10’s intended workloads—a departure from previous advantages seen with POWER8 and POWER9 platforms.
Variants
Power10 processors come in two firmware-configured versions—identical physical chips distinguished solely by the firmware programmed during manufacturing:
- 15× SMT8 cores: designed for workloads favoring high throughput with moderate computational demands
- 30× SMT4 cores: tailored for tasks requiring intensive computation with complex instructions and multiple cache accesses
Modules
Power10 is available in three FC-PLGA module types: a single chip module (SCM) and two dual-chip modules (DCM and eSCM).
- SCM – operates between 3.6 and 4.15 GHz, supports up to 15 SMT8 cores; scalable to clusters with as many as 16 sockets; equipped with 32 PCIe 5 lanes; module dimensions are 68.5×77.5 mm and include eight SMP connectors for direct inter-module communication.
- DCM – runs from 3.4 to 4.0 GHz, accommodates up to 24 SMT8 cores; clusters can include up to four sockets; provides 64 PCIe 5 lanes; measures 74.5×85.75 mm; offered in four variants targeting different performance needs, including options specialized for healthcare applications.
- eSCM – entry-level single chip module operating at 3.0-3.9 GHz with up to 8 SMT8 cores; integrates two Power10 chips—one fully active with processing cores, the other dedicated to PCIe switching and additional lanes; supports clustering of up to four sockets; shares size specifications with the DCM; also referred to as "ioscm".
Enterprise
IBM's premier Power10 server is the IBM Power E1080, codenamed Denali. It consists of 1 to 4 Central Electronics Complex (CEC) nodes, each occupying 5U of rack space. Every node houses four Power10 SCM processors, configurable with either 10, 12, or 15 SMT8 cores per processor, and supports up to 16 TB of OMI-DDR4 memory. The platform runs PowerVM virtualization software compatible with AIX, IBM i, and little-endian Linux. A separate System Control Unit in a 2U form factor is required for management and configuration.
The Power E1080 can connect up to sixteen I/O expansion drawers—four per CEC node—via PCIe fanout modules. Each drawer offers twelve FHFL PCIe slots: four PCIe 3.0 x16 and eight PCIe 3.0 x8 slots. At full capacity, the system supports a maximum of 192 single-slot PCIe cards distributed across sixteen sockets.
Mid-range
- IBM Power E1050 - housed within a 4U chassis featuring between two and four CPU sockets supporting an equal number of DCM modules, delivering from 24 to 96 cores. It includes sixty-four OMI memory slots allowing up to 16 TB of RAM, eleven PCIe slots (eight Gen5 and three Gen4), plus ten NVMe SSD slots with a maximum capacity of 64 TB. The system supports Linux, AIX, and IBM i operating systems.
Scale-out
S-model servers support Linux, IBM i, and AIX operating systems; L-models primarily run Linux but permit AIX and IBM i on up to one-quarter of CPU cores.
- IBM Power S1024 & L1024 - configured in a 4U chassis containing one or two CPU sockets (24-48 cores), thirty-two OMI memory slots supporting as much as 8 TB RAM, and ten PCIe slots (eight Gen5 and two Gen4). Storage options include up to 102 TB NVMe SSDs across sixteen slots.
- IBM Power S1022 & L1022 - housed in a compact 2U chassis with one or two CPU sockets (24-40 cores), thirty-two OMI memory slots supporting up to 4 TB RAM, and ten PCIe slots (eight Gen5 and two Gen4). Storage capacity reaches up to 51 TB NVMe SSDs via eight slots.
- IBM Power S1022s - a smaller form factor 2U system utilizing one or two eSCM modules (offering between four and sixteen cores), sixteen OMI memory slots supporting as much as 2 TB RAM, maintaining similar PCIe and storage configurations as the S1022 model.
- IBM Power S1014 - available both as a 4U rackmount or deskside tower chassis featuring a single eSCM module (with either four or eight cores), eight OMI memory slots supporting up to 1 TB RAM, five PCIe slots (four Gen5 and one Gen4), and storage capacity supporting up to 102 TB NVMe SSDs.
- IBM Power S1012 - half-wide chassis available in either a 2U rackmount or deskside tower format, equipped with one eSCM module (configurable with one, four, or eight cores), four OMI memory slots supporting up to 256 GB RAM, four PCIe Gen5 slots, and storage options accommodating up to 6.4 TB NVMe SSDs.
Operating system compatibility
Comparison to previous POWER processors
Transitioning to a 7-nanometer manufacturing technology results in notably improved performance efficiency.
The PowerAXON architecture now accommodates up to 2 PB of shared clustered memory spanning multiple cluster nodes and incorporates support for PCIe 5.
Enhanced AI processing is enabled by the introduction of new SIMD instructions and data formats including bfloat16, INT4, and INT8.
In contrast to POWER8 and POWER9, Power10 mandates proprietary third-party firmware for its security-sensitive CPU components and the off-module memory controller.
Brand identity
With Power10, IBM shifts from former naming styles by using lowercase letters, aligning with the rebranding of its Power Systems product line to simply "Power" starting from this generation. Additionally, Power10 is distinguished by a unique logo design.