Alpha 21066

Digital Equipment Corporation
Company type	Company
Industry	Computer hardware, Microprocessors
Headquarters	Hudson, Massachusetts and South Queensferry, Scotland (semiconductor plants), United States, United Kingdom
Area served	Worldwide
Key people	Dirk Meyer (micro-architect), Edward McLellan (micro-architect), Jim Montanaro (circuit implementation manager)
Products	Alpha 21064 microprocessor, Alpha 21064A, Alpha 21164, Alpha 21066, Alpha 21068

The Alpha 21064 is a microprocessor developed and produced by Digital Equipment Corporation that implements the Alpha (initially known as Alpha AXP) instruction set architecture (ISA). Originally introduced under the name DECchip 21064 before its renaming in 1994, it is also identified by the codename EV4. Announced in February 1992 and reaching mass production by September of the same year, this was Digital's inaugural commercial microprocessor based on the Alpha ISA. The Alpha 21064 was later succeeded by the Alpha 21064A in October 1993, which in turn was replaced by the Alpha 21164 in 1995.

History

The first Alpha processor was a prototype chip known as EV3, fabricated using Digital’s 1.0-micrometre CMOS-3 technology. This early version lacked a floating point unit and contained only 1 KB of cache, serving primarily to validate advanced circuit design approaches and to support firmware and operating system development efforts.

The production-ready chip, designated EV4, was manufactured with Digital’s 0.75 μm CMOS-4 process. The design team was led by micro-architects Dirk Meyer and Edward McLellan, with circuit implementation managed by Jim Montanaro. The EV3 powered the Alpha Demonstration Unit (ADU), a multiprocessor platform created for software development before the EV4 became available.

At the 39th International Solid-State Circuits Conference held in February 1992, the 150 MHz sample was introduced with pricing tiers of $3,375 for orders of 100 units, $1,650 for quantities between 100 and 1,000, and $1,560 for orders exceeding 1,000 units. Volume production began in September of that year. By February 1993, bulk pricing for orders over 1,000 units had decreased to $1,096.

A faster 200 MHz variant was launched on February 25, 1993, with sample kits priced at $3,495 and volume pricing set at $1,231 per unit for orders above 10,000. Shipments at scale commenced in August 1993. Concurrently, the price for the 150 MHz model fell to $853 for large volume purchases by July.

After releasing the Alpha 21066 and Alpha 21068 on September 10, 1993, Digital adjusted its product lineup by introducing a new 166 MHz model priced at $499 per unit for orders exceeding 5,000 units while reducing the cost of the 150 MHz chip to $455.

On June 6, 1994, further price reductions were implemented: the cost of the 200 MHz processor dropped by 31% to $544 to better compete with the 60 MHz Pentium processor, and the price of the 166 MHz version decreased by 19% to $404 per unit for quantities over 5,000 units effective from July.

Digital Equipment Corporation remained the exclusive manufacturer without any secondary sourcing arrangements. The Alpha 21064 chips were produced at Digital’s semiconductor plants located in Hudson, Massachusetts and South Queensferry, Scotland.

Users

The primary applications for the Alpha 21064 were high-performance workstations and servers. Notable adopters included:

Aspen Systems utilizing it in their Alpine workstation series
Carrera Computers employing it in Hercules 150, Hercules 200, and Pantera II workstation models
Cray Research, which integrated the 150 MHz variant into their Cray T3D supercomputers
Digital itself incorporating it across entry-level to high-end systems such as DECpc AXP 150, DEC 2000 AXP, DEC 3000 AXP, DEC 4000 AXP, and DEC 7000/10000 AXP servers and workstations
Encore Computer using it within their Infinity R/T line of high-end real-time computing systems

Performance

At the time of its launch, the 21064 was the leading microprocessor in terms of performance until IBM released the multi-chip POWER2 in 1993. It held the title of the fastest single-chip microprocessor until October 1993, when the 275 MHz 21064A was introduced.

Description

The Alpha 21064 is a superpipelined, dual-issue superscalar processor that executes instructions sequentially. It can issue up to two instructions per clock cycle through four distinct functional units: integer, floating-point (FPU), address, and branch units. The integer pipeline consists of seven stages, while the floating-point pipeline spans ten stages, with the initial four stages shared and implemented within the I-box.

I-box

Functioning as the control unit, the I-box handles instruction fetching, decoding, issuing, and pipeline management. During the first stage, two instructions are fetched from the instruction cache (I-cache). Branch prediction takes place in stage two using either static or dynamic techniques. Static prediction determines backward branches as taken based on the sign bit of branch displacement; dynamic prediction relies on a 2,048-entry one-bit branch history table achieving approximately 80% accuracy. A branch misprediction incurs a penalty of four cycles.

Instructions undergo decoding in stage three. In stage four, the I-box checks resource availability for issuing instruction pairs according to integer register file port constraints. Permissible pairings include an integer operate with a floating-point operate, any load/store paired with an operate instruction, an integer operate combined with an integer branch, or a floating-point operate with a floating-point branch. Pairings such as integer operate with floating-point store or floating-point operate with integer store are prohibited. If pairing is not feasible or resources are insufficient, the first four pipeline stages stall until issuance conditions are satisfied.

The I-box incorporates two fully associative instruction translation buffers (ITBs) for virtual-to-physical address translation: an eight-entry ITB dedicated to 8 KB pages and a four-entry ITB for 4 MB pages. Both employ a not-last used replacement strategy to cache recent page table entries relevant to instruction streams.

Execution

Execution begins at stage five for all instructions, with register file reads occurring in stage four. Pipelines starting at stage five are non-stallable.

Integer unit

The integer unit processes integer instructions and comprises the integer register file (IRF) and the E-box. The IRF contains thirty-two 64-bit registers equipped with four read ports and two write ports shared between the integer and branch units. The E-box includes components such as an adder, logic unit, barrel shifter, and multiplier. Most integer instructions complete by stage five with a latency of one cycle, except for multiply, shift, and byte manipulation operations. Shift and byte instructions complete by stage six with a two-cycle latency. To conserve die area, the multiplier is not pipelined, resulting in multiply operations that take between 19 and 23 cycles to complete. Results are written back to the IRF during stage seven.

Address unit

The address unit ("A-box") handles load/store instructions and operates concurrently with the integer unit by utilizing its own displacement adder for virtual address computation. It features a 32-entry fully associative translation lookaside buffer (TLB), known as the data translation buffer (DTB), which supports 43-bit virtual addressing (8 TB) and 34-bit physical addressing (16 GB). Store instructions utilize a write buffer consisting of four entries of 32 bytes each that merges adjacent stores and postpones writes to enhance performance by reducing bus traffic and speeding up load operations.

Floating-point unit

The floating-point unit incorporates a floating-point register file (FRF) consisting of thirty-two 64-bit registers, equipped with three read ports and two write ports. It also includes the F-box, which houses a floating-point pipeline alongside a non-pipelined divider that completes one bit per cycle. During the fourth stage, data is segmented into fraction, exponent, and sign components. Add instructions compute the difference between exponents and trigger normalization, while multiply instructions produce a 3× multiplicand value.

Stages five and six are responsible for alignment, normalization shifts, sticky-bit computations, and multiplication through a pipelined, two-way interleaved radix-8 Booth multiplier array. The final addition and rounding are performed in stage eight. Floating-point results are written back to the FRF in stage ten. The pipeline latency for floating-point operations is six cycles; however, the non-pipelined division unit requires 31 cycles for single-precision and 61 cycles for double-precision divides.

Caches

The 21064 processor integrates two on-chip primary caches: an 8 KB data cache (D-cache) with a write-through policy and an 8 KB instruction cache (I-cache). Both caches utilize a direct-mapped architecture allowing single-cycle access and feature a 32-byte line size. They are constructed using six-transistor SRAM cells occupying an area of 98 μm² each. The cache arrays span 1,024 cells in width by 66 cells in height, with the uppermost two rows reserved for redundancy purposes.

An optional external secondary cache (B-cache) supports sizes ranging from 128 KB up to 16 MB. This cache operates at frequencies between one-third and one-sixteenth of the internal clock speed (12.5 to 66.67 MHz when the internal clock is at 200 MHz). It is direct-mapped by default with a 128-byte line size but can be configured for larger block sizes. The B-cache interfaces through the system bus.

External interface

The processor’s external interface comprises a 128-bit data bus that functions at speeds from half down to one-eighth of the internal clock frequency (25 to 100 MHz at a 200 MHz internal clock), with configurability down to 64 bits. Additionally, it includes a 34-bit wide address bus.

Fabrication

Containing approximately 1.68 million transistors, the 21064 was manufactured using Digital’s CMOS-4 process technology featuring a 0.75 μm fabrication node and three layers of aluminium interconnects. The EV4 die measures 13.9 mm by 16.8 mm, totaling an area of 233.52 mm². A subsequent iteration, the EV4S, was produced via a roughly 10% optical shrink to CMOS-4S technology at a 0.675 μm feature size, resulting in die dimensions of 12.4 mm by 15.0 mm (186 mm²).

Operating at a voltage supply of 3.3 volts, the EV4 dissipates up to 30 watts when running at 200 MHz; in comparison, the EV4S consumes between 21 watts at 150 MHz and up to 27 watts at 200 MHz.

Package

The chip is packaged within a 431-pin alumina-ceramic pin grid array (PGA) measuring approximately 61.72 mm square. Of these pins, 291 are dedicated to signals while the remaining 140 serve power and ground connections. The heatsink is affixed directly onto the package using nuts secured on studs that extend from a tungsten heat spreader.

Alpha 21064A

The Alpha 21064A, also known as the DECchip 21064A and codenamed EV45, represents an improved iteration of the Alpha 21064 launched in October 1993. It was available in clock speeds including 200, 225, 233, 275, and 300 MHz variants. On July 6, 1994, the original 225 MHz model was replaced by a faster 233 MHz version priced at US$788 per unit for orders of 5,000 units—a reduction of approximately ten percent relative to its predecessor. Simultaneously, the price of the 275 MHz model decreased by twenty-five percent to US$1,083 per unit. The fastest variant running at 300 MHz was announced in October of 1995 and began shipping by December that year. A specialized version labeled the 21064A-275-PC was designed exclusively for Windows NT or compatible operating systems.

As Digital’s flagship Alpha microprocessor during its time, the Alpha 21064A powered numerous high-performance systems such as Digital’s DECstation series including DECstation AXP models: DECstation AXP/3000, AXP/4000, and AXP/7000/10000 families. Other notable adopters encompassed Aspen Systems’ Alpine workstation line, BTG’s Action AXP275 RISC PC, Carrera Computers’ Cobra AXP275 workstation series, NekoTech’s Mach model overclocked to approximately 289 MHz (Mach 2-289-T), as well as Network Appliance’s storage products.

Key microarchitectural improvements over its predecessor involved doubling both instruction and data primary cache capacities from eight kilobytes to sixteen kilobytes each while adding parity error detection capabilities. The floating-point divide unit was enhanced to retire two bits per cycle on average, reducing divide latency significantly. Branch prediction performance improved through expansion of the branch history table from its original size to a larger structure holding four thousand ninety-six entries with two-bit saturating counters.

The die contained approximately 2.8 million transistors within dimensions measuring roughly 14.5 mm by 10.5 mm (152.25 mm²). Fabrication utilized Digital’s fifth-generation CMOS-5 process technology featuring a half-micron (0.5 μm) design rule with four levels of aluminium interconnect layers.

Alpha 21066

The Alpha 21066, also known as the DECchip 21066 and internally referred to as LCA4 (Low Cost Alpha), represents an affordable iteration of the Alpha 21064, introduced in September 1993 with mass production commencing in early 1994. The initial model operated at 166 MHz and was priced at US$385 per unit for orders of 5,000 pieces. A slower 100 MHz variant was developed for embedded system applications, with sample units available from late 1994 and volume deliveries by the third quarter of 1995. This processor was notable as the first to incorporate a PCI controller on-chip.

Engineered primarily for budget-sensitive uses—especially personal computers running Windows NT—the Alpha 21066 was implemented in Digital’s Multia client systems, AXPpci OEM motherboards, and AXPvme single-board computers. Additional adopters included Aspen Systems’ Alpine workstation, Carrera Computers’ Pantera I workstation, NekoTech’s Mach 1-166 PC, and Parsys’ TransAlpha TA9000 supercomputers.

By utilizing a die shrink process, the design integrated features advantageous for embedded environments: an on-chip B-cache and memory controller with ECC support; a modest graphics accelerator capable of addressing up to 8 MB of VRAM for framebuffer use; a PCI controller; and a PLL clock generator that multiplied an external 33 MHz clock to reach internal operating frequencies.

The memory controller accommodated B-cache sizes ranging from 64 KB up to 2 MB and supported main memory capacities between 2 and 512 MB. Its ECC functionality enabled detection of multiple-bit errors while correcting single-bit faults. To minimize expenses and reduce package dimensions, the system bus width was narrowed to 64 bits, which lowered bandwidth and performance by approximately 20%—a trade-off deemed acceptable within its intended market segments.

This microprocessor housed roughly 1.75 million transistors on a die measuring 17.0 by 12.3 mm (totaling 209.1 mm²), manufactured using the CMOS-4S process—a 0.675 μm technology featuring three metal interconnect layers—and was enclosed in a 287-pin CPGA package measuring about 57.4 by 57.4 mm.

Alpha 21066A

The Alpha 21066A, bearing the codename LCA45, is an economical version derived from the Alpha 21064A. It was unveiled on 14 November 1994 with initial models running at 100 and 233 MHz, which began shipping in March 1995 at prices of $175 and $360 respectively for orders of 5,000 units. Subsequently, a faster 266 MHz variant was introduced.

Mitsubishi Electric became a secondary manufacturer of the 21066A under the designation M36066A, marking its inaugural fabrication of Alpha processors. Announced concurrently with Digital’s offerings, Mitsubishi scheduled engineering samples for December 1994 and aimed for volume manufacturing by September 1995, pricing their 233 MHz chip at $490 per batch of 1,000 units.

In contrast to the Alpha 21064A, the Alpha 21066A eliminated the separate 16 KB instruction and data caches but incorporated software-controlled power management features that allowed dynamic adjustment of clock frequencies.

Digital deployed various configurations of the 21066A within products that had formerly utilized the original 21066. Tadpole Technology incorporated the 233 MHz variant into its ALPHAbook 1 laptop computer.

This processor contains approximately 1.8 million transistors on a die area of about 161.32 mm², fabricated using Digital’s CMOS-5 process (0.5 μm) with three metal interconnect layers. Mitsubishi produced its version employing a comparable three-level-metal process at the same feature size.

Alpha 21068

The Alpha 21068 (also known as DECchip 21068) was designed for embedded applications, sharing similarities with the 21066 but operating at a reduced clock speed to lower both power consumption and cost. Sample units were first distributed in September 1993, with full production commencing in early 1994. It ran at 66 MHz and had a peak power dissipation of 9 W. Initially, the chip was priced at $221 per unit for orders of 5,000, but Digital reduced this price by 16% to $186 in July 1994.

Digital incorporated the Alpha 21068 into its AXPpci 33 motherboard and AXPvme single-board computer platforms.

Alpha 21068A

The Alpha 21068A (DECchip 21068A) represents an embedded system version derived from the Alpha 21066A, featuring a clock speed of 100 MHz.

Chipsets

At first, there was no standard chipset available for the 21064 and 21064A processors, leading Digital to utilize custom ASICs for system interfacing purposes. To alleviate development expenses for original equipment manufacturers (OEMs), Digital launched the DECchip 21070 chipset, also referred to as Apecs.

The DECchip 21070 chipset was offered in two variants: the 21071, intended for workstation use, and the 21072, aimed at high-end workstations or entry-level uniprocessor servers. The primary distinction between them lay in memory support capabilities—the 21071 featured a 64-bit memory bus accommodating between 8 MB and 2 GB of parity-protected memory, whereas the 21072 provided a wider 128-bit bus supporting from 16 MB up to 4 GB of ECC-protected memory.

This chipset consisted of three main components: the COMANCHE B-cache and memory controller, DECADE data slices, and the EPIC PCI controller. The DECADE chips implemented data pathways using 32-bit slices—two chips were employed in the 21071 version and four in the 21072—while EPIC managed a 32-bit interface connecting to DECADE.

Announced on January 10, 1994, samples became available shortly thereafter with mass shipments planned for mid-year. Pricing was set at $90 for the 21071 and $120 for the 21072 when purchased in quantities of 5,000 units.

Among its adopters were Carrera Computers for their Pantera workstation line and Digital itself in certain AlphaStation models as well as uniprocessor AlphaServer systems.

History

Users

Performance

Description

I-box

Execution

Integer unit

Address unit

Floating-point unit

Caches

External interface

Fabrication

Package

Alpha 21064A

Alpha 21066

Alpha 21066A

Alpha 21068

Alpha 21068A

Chipsets

Further reading